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US 6,605,498 B1Granted
Semiconductor transistor having a backfilled channel material
AssigneeIntel Corporation
InventorsAnand S. Murthy, Brian S. Doyle, Brian E. Roberds
Life of this patent
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Abstract
A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.
Claims20
A semiconductor transistor comprising:
- a layer having a surface of a semiconductor material having a first lattice with a first structure and a first spacing;
- a channel material, which:
- (a) includes a channel dopant to have a first conductivity type;
- and
- (b) is formed epitaxially on the surface to have a second lattice with a second structure which is the same as the first structure, the second lattice having a second spacing which is different than the first spacing;
- source and drain regions on opposite sides of at least a portion of the channel material, including source/drain dopants to have a second conductivity type which is opposite to the first conductivity type;
- a gate dielectric material on the channel material;
- and
- a conductive gate electrode on the gate dielectric material.
6 more elements
A semiconductor transistor comprising:
- a layer with a surface of a semiconductor material having a first lattice with a first structure and a first spacing;
- a channel material, which:
- (a) includes a channel dopant to have a first conductivity type selected from one of (i) an n-dopant conductivity type and (ii) a p-dopant conductivity type;
- and
- (b) is formed epitaxially on the surface to have a second lattice with a second structure which is the same as the first structure, the second lattice having a second spacing which (i) is larger than the first spacing if the first conductivity type is an n-dopant conductivity type and (ii) is smaller than the first spacing if the first conductivity type is a p-dopant conductivity type;
- source and drain regions on opposite sides of at least a portion of the channel material, including source/drain dopants to have a second conductivity type which (i) is a p-dopant conductivity type if the first conductivity type is an n-dopant conductivity type and (ii) is an n-dopant conductivity type if the first conductivity type is a p-dopant conductivity type;
- a gate dielectric material on the channel material;
- and
- a conductive gate electrode on the gate dielectric material.
6 more elements
A method of making a semiconductor transistor, comprising:
- forming a gate dielectric layer over a semiconductor substrate;
- forming a gate electrode on the gate dielectric layer;
- etching the semiconductor substrate to form a channel recess;
- filling the channel recess with a channel material that includes channel dopants to have a first conductivity type;
- and
- forming source and drain regions on opposite sides of at least a portion of the channel material, the source and drain regions having a second conductivity type opposite to the first conductivity type.
3 more elements
Dependencies are inferred from the claim text.