US 6,604,230 B1Granted

Multi-logic device systems having partial crossbar and direct interconnection architectures

AssigneeThe Governing Counsel of the University of Toronto

InventorsMohammed A. S. Khalid, Jonathan Rose

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Abstract

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. The architecture disclosed uses a mixture of hardwired and programmable connections for interconnecting the FPGAs. A hardwired connection is a direct connection between a pair of FPGA I/O pins. A programmable connection refers to the scheme in which pair of FPGA I/O pins are connected using an programmable interconnect device. In the architecture disclosed, the I/O pins in each FPGA are divided into two groups: hardwired connections and programmable connections. The pins in the first group connect to other FPGAs and the pins in the second group connect to FPIDs. The FPGAs and FPIDs are interconnected using a partial crossbar architecture.

Claims13

Dependent claims

An electrically reconfigurable logic assembly comprising:

a printed circuit board, said printed circuit board comprising a plurality of fixed electrical conductors, said plurality of fixed electrical conductors segregated into at least a first set of fixed electrical conductors and a second set of fixed electrical conductors;
a plurality of reprogrammable logic devices disposed on said printed circuit board, each of said plurality of reprogrammable logic devices comprising configurable logic elements, each of said plurality of reprogrammable logic devices also comprising logic device input/output terminals, said logic device input/output terminals reprogrammably connectable to selected ones of said plurality of configurable logic elements;
a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having interconnect device input/output terminals and internal circuitry, said internal circuitry reprogrammably configurable to provide interconnections between selected ones of said interconnect device input/output terminals;
said first set of fixed electrical conductors connecting a first group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said interconnect device input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said first group of said logic device input/output terminal on each of said plurality of reprogrammable logic devices;
and
said second set of fixed electrical conductors connecting a second group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said second group of logic device input/output terminals on every other of said plurality of reprogrammable logic devices, such that each of said plurality of reprogrammable logic devices is in direct electrical communication with every other of said plurality of reprogrammable logic devices on said printed circuit board.

3 more elements

An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system that is configurable with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:

a plurality of reprogrammable logic devices, each said plurality of reprogrammable logic devices comprising a plurality of configurable logic elements, each of said plurality of reprogrammable logic devices also having also having logic device input/output terminals, said logic device input/output terminals reprogrammably connectable to selected ones of said configurable logic elements, said logic device input/output terminals subdivided into a least a first group of logic device input/output terminals and a second group of logic device input/output terminals;
a plurality of reprogrammable interconnect devices, each of said reprogrammable interconnect devices having a plurality of interconnect device input/output terminals and internal circuitry, said internal circuitry reprogrammably configurable to provide interconnections between selected ones of said interconnect device input/output terminals on said plurality of reprogrammable interconnect devices;
a first set of fixed electrical conductors connecting said first group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said interconnect device input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said logic device input/output terminals of said first group of said logic device input/output terminals on each of said plurality of reprogrammable logic device;
a second set of fixed electrical conductors connecting said second group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said second group of logic device input/output terminals on every other of said plurality of reprogrammable logic devices, such that each of said plurality of reprogrammable logic devices is in direct electrical communication with every other of said plurality or reprogrammable logic devices;
and
an interface structure arranged to provide signal paths for signals carrying information to or from designated ones of said configurable logic elements in said reprogrammable logic devices.

3 more elements

Dependencies are inferred from the claim text.