Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools

A minimal level sensitive timing abstraction model comprising:

• an input port that represents an input in a circuit, wherein the circuit includes sequential elements controlled by internally generated clock signals;
• an output port that represents an output in the circuit;
• a check node connected to the input port, wherein the check node establishes a required time;
• and
• a dummy latch node connected to the output port, wherein the dummy latch node is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port,
• wherein the dummy latch node enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the dummy latch node, and
• wherein the timing abstraction model is stimulus independent, port-based, and has no internal latch nodes, and models a circuit block by extracting a plurality of parameters from said circuit that includes sequential elements controlled by internally generated clock signals.

A computer readable medium providing instructions for modeling a circuit block with a minimal level sensitive timing abstraction model, the instructions comprising:

• modeling a circuit block by extracting a plurality of parameters from a circuit that includes sequential elements controlled by internally generated clock signals, wherein the extracting step comprises:
• for each input port associated with an input in the circuit, extracting a required time parameter associated with a check node;
• for each output port associated with an output in the circuit, extracting a valid time parameter associated with a dummy latch node, wherein the valid time parameter traces a latest clock signal arriving at the output port, and wherein the dummy latch node is controlled by an internally generated clock signal that becomes active when the latest clock signal from the circuit arrives at the output port;
• and
• extracting an input-to-output delay parameter that represents a time delay a signal passes from the input port to the output port,
• wherein the dummy latch node enables the signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the dummy latch node;
• and
• creating an echo-circuit that represents the plurality of parameters, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and is used in any static timing analysis (STA) tools.