Telecommunications system and method for supporting an incremental redundancy error handling scheme using available gross rate channels

A transmitter for supporting an error handling scheme using at least one available gross rate channel, said transmitter comprising:

• a coding circuit for coding a digital data block and generating a mother code word,
• a reordering circuit for reordering the mother code word and generating a reordered mother code word, wherein the reordered mother code word is generated based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver;
• and
• a modulating circuit for modulating a subsequence taken from a first sequence of bits in the reordered mother code word and for forwarding the modulated first subsequence to the receiver using the available bandwidth of a first available gross rate channel, said modulating circuit being further capable of repeating the process of modulating and forwarding other subsequences taken from the reordered mother code word until the receiver successfully decodes the digital data block.

A method for supporting an incremental redundancy error handling scheme using at least one available gross rate channel, said method comprising the steps of:

• coding a digital data block to generate a mother code word;
• reordering the mother code word to generate a reordered mother code word, wherein the reordered mother code word is generated based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver;
• and
• modulating at least one subsequence from the reordered mother code word and forwarding the at least one modulated subsequence to the receiver using the available bandwidth of the at least one available gross rate channel.

A wireless communications system comprising:

• a receiver;
• a transmitter operatively coupled to said receiver, said transmitter including:
• a coding circuit for coding a digital data block and generating a mother code word;
• a reordering circuit for reordering the mother code word and generating a reordered mother code word, wherein the mother code word is reordered based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to the receiver;
• and
• a modulating circuit for modulating a first subsequence taken from a first sequence of bits in the reordered mother code word and forwarding the modulated first subsequence to the receiver in the available bandwidth of a first available gross rate channel, said modulating circuit being further capable of modulating a second subsequence taken from a second sequence of bits in the reordered mother code word and forwarding the modulated second subsequence to the receiver in the available bandwidth of a second available gross rate channel, said modulating circuit also being capable of repeating the process of modulating and forwarding additional subsequences taken from additional sequences of bits in the reordered mother code word until the receiver successfully decodes the digital data block.

A transmitter comprising:

• a coding circuit for coding a digital data block and generating a mother code word;
• a reordering circuit for reordering the mother code word according to an ordering vector based on at least one puncturing pattern and generating a reordered mother code word, wherein the ordering vector defines an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver;
• and
• a modulating circuit for modulating at least one subsequence from the reordered mother code word and forwarding the at least one modulated subsequence to the receiver using at least one fixed net rate channel, wherein said at least one subsequence has as many bits as needed to obtain a desired code rate in view of at least one quality of service requirement.