Method and apparatus for determining a minimum clock delay in a memory
AssigneeSTMicroelectronics S.r.l.
InventorHenry Nurser
Life of this patent
Estimating the term…
Abstract
An apparatus and method for determining a minimum clock delay provided to sense amplifiers of a memory array. The method first determines a response time of the overall memory circuit by varying the delay of an external clock until the output of the memory circuit is just valid. Then an externally provided sense amplifier clock is substituted for the internal sense amplifier clock and the instant of application of the externally provided sense amplifier clock is varied until the circuit output is just valid.
Claims13
A method of operating a device, the device comprising circuitry having an input responsive to a first timing signal and producing a valid output to clocked output circuitry after a first delay, said clocked output circuitry having a clock node, and a clock delay circuit responsive to said first timing signal for providing after a second delay, a second timing signal to said clock node of said clocked output circuitry, the method comprising:
- repeatedly applying said first timing signal followed by an external timing signal, wherein said external timing signal is applied via a delay-producing first path to said clock node;
- monitoring an output of said clocked output circuitry;
- varying the delay produced by said delay-producing first path to vary the delay of application of said external timing signal with respect to said first timing signal;
- and
- in response to a desired output of said clocked output circuitry, modifying said second delay.
A method of determining a minimum sense amplifier clock delay in a memory, the memory comprising address register circuitry having a clock input, an array of memory cells having wordlines coupled to said address register circuitry and bitlines connected to sense amplifier circuitry, said sense amplifier circuitry having a clock input, the memory further having output circuitry having an input coupled to the output of said sense amplifier circuitry and an output, the method comprising:
- providing a first path having an input, said first path having an output coupled to said clock input of said address register circuitry;
- providing a second path having an input, said second path having an output coupled to said clock input of said sense amplifier circuitry;
- repeatedly applying first timing signals at said input of said first path and at a variable delay after each said application, applying a second timing signal at said input of said second path;
- and
- evaluating conditions at said output of said output circuitry.
A testing device for a memory, said memory having address register circuitry having an address register clock node, a memory array and sense amplifier circuitry having a sense amplifier clock node and a sense amplifier output, said testing device comprising a first timing signal generator coupled to said address register clock node via a first path for clocking said address register circuitry, a sense amplifier clock generator responsive to a signal at said address register clock node for producing a first sense amplifier clock signal, a second timing signal generator coupled to said sense amplifier clock node for providing a second sense amplifier clock signal, clocking and selector circuitry for selectably coupling said first or said second sense amplifier clock signal, to said sense amplifier clock node, said device further comprising means for varying the timing of said second sense amplifier clock signal with respect to said first timing signal.
Dependencies are inferred from the claim text.