Reduced GMII with internal timing compensation

A data interface between first and second integrated circuits, comprising:

• a clock input on the first integrated circuit for receiving a clock signal generated internal to the second integrated circuit and transmitted therefrom;
• a receive data input on the first integrated circuit for receiving data generated internal to the second integrated circuit and transmitted therefrom, said data generated internal to the second integrated circuit synchronized with said receive clock on said clock input of the first integrated circuit;
• and
• a first delay block internal to the first integrated circuit for delaying the received clock on said clock input on the first integrated circuit by a predetermined duration of one clock cycle of said receive clock from the second integrated circuit to provide a first delayed clock;
• wherein said first delayed clock is utilized by the first integrated circuit to sample the data received on said receive data input.

A system having at least first and second integrated circuits associated therewith, with data transferred therebetween, comprising:

• an internal clock signal internal to the first integrated circuit and operating at a first frequency;
• a data generator for generating data from at least one edge of said internal clock for transmission to the second integrated circuit through a data output on the first integrated circuit to a data terminal;
• a data input on the second integrated circuit for receiving the data output from the first integrated circuit;
• a first delay block internal to the first integrated circuit for delaying said internal clock for a predetermined duration of one clock cycle of said internal clock to provide a first delayed clock through a clock output on the first integrated circuit;
• a clock input on the second integrated circuit for receiving the first delayed clock;
• and
• a sampling circuit on the second integrated circuit for utilizing the transmitted first delayed clock to sample received data on data input thereon that was received from the data output of the first integrated circuit, which was generated by said data generator.

A method for interface data between first and second integrated circuits, comprising the steps of:

• generating an internal clock signal internal to the first integrated circuit and operating at a first frequency;
• generating data with a data generator from at least one edge of the internal clock for transmission to the second integrated circuit through a data output on the first integrated circuit to a data terminal;
• and
• delaying the internal clock with a first delay block internal to the first integrated circuit for a predetermined duration of one clock cycle of the internal clock to provide a first delayed clock through a clock output on the first integrated circuit;
• wherein the second integrated circuit is operable to receive the transmitted first delayed clock on a clock input terminal thereon and utilize the transmitted first delayed clock to sample data on a data input thereon that was received from the data output of the first integrated circuit, which was generated by the data generator.

A method for interfacing between first and second integrated circuits, comprising:

• receiving on a clock input on the first integrated circuit a clock signal generated internal to the second integrated circuit and transmitted therefrom;
• receiving on a receive data input on the first integrated circuit data generated internal to the second integrated circuit and transmitted therefrom, the data generated internal to the second integrated circuit synchronized with the receive clock on the clock input of the first integrated circuit;
• and
• delaying with a first delay block internal to the first integrated circuit the received clock on the clock input on the first integrated circuit by a predetermined duration of one clock cycle of the receive clock from the second integrated circuit to provide a first delayed clock;
• wherein the first delayed clock is utilized by the first integrated circuit to sample the data received on the receive data input.

A method for interfacing first and second integrated circuits for data transfer therebetween, comprising the steps of:

• generating an internal clock signal internal to the first integrated circuit and operating at a first frequency;
• generating data with a data generator from at least one edge of the internal clock for transmission to the second integrated circuit through a data output on the first integrated circuit to a data terminal;
• receiving on a data input on the second integrated circuit the data output from the first integrated circuit;
• delaying with a first delay block internal to the first integrated circuit the internal clock for a predetermined duration of one clock cycle of the internal clock to provide a first delayed clock through a clock output on the first integrated circuit;
• receiving the first delayed clock on a clock input on the second integrated circuit;
• and
• sampling the received data on the data input to the second integrated circuit that was received from the data output of the first integrated circuit with the transmitted first delayed clock.