Low power processor
AssigneeHitachi, Ltd.
InventorsOsamu Nishii, Masayuki Miyazaki, Kiyoo Itoh
Life of this patent
Estimating the term…
Abstract
In order to save a sub-threshold leak current during operation of processor, a decision circuit (instruction decoder) inputs an instruction signal and outputs an operation mode signal regarding the level of a leak current based on information about use of the circuit block. Thereby, a sub-threshold leak current in the circuit block not used can be saved.
Claims17
A processor which executes an instruction included in an instruction set, comprising:
- a plurality of circuit blocks, each of circuit blocks including a first insulated-gate field-effect transistor;
- an instruction decoder which decodes the instruction and generates a control signal for controlling an operating condition of the circuit block;
- and
- a transfer line which transfers the control signal;
- wherein the control signal is transferred so that a circuit block respectively used in a particular pipeline stage receives the control signal according to the particular pipeline stage,
- each of the plurality of circuit blocks is set to the first operation condition depending on receiving the control signal from the second operation condition,
- first current flows through source-drain path of the first insulated-gate field-effect transistor even when a source-gate voltage is set 0V in the first operating condition, and
- second current lower than the first current flows through source-drain path of the first insulated-gate field-effect transistor even when the source-gate voltage is set 0V in the second operating condition.
A method of reducing a power consumption of a processor which executes an instruction included in an instruction set, comprising:
- providing the processor comprising a plurality of circuit blocks, each of the circuit blocks including a first insulated-gate field-effect transistor;
- decoding the instruction;
- generating a control signal for controlling an operating condition of the circuit block;
- transferring the control signal to a circuit block respectively used in a particular pipeline stage;
- and
- setting an operating condition of the circuit block respectively used in a particular pipeline stage according to receipt of the control signal from a second operating condition to a first operating condition;
- wherein first current flows through source-drain path of the first insulated-gate field-effect transistor even when a source-gate voltage is set 0V in the first operating condition, and
- second current lower than the first current flows through source-drain path of the first insulated-gate field-effect transistor even when the source-gate voltage is set 0V in the second operating condition.
A processor comprising a plurality of circuit blocks used by the instruction signal included in the instruction set and an instruction decoder for decoding said instruction signal to output a control signal for designating use of a plurality of said circuit blocks;
- wherein
- a plurality of said circuit blocks are used respectively in the predetermined pipeline stage and said control signal is transferred in synchronization with said pipeline stage;
- a plurality of said circuit blocks include a complimentary MOSFET having a first P-channel MOSFET and a first N-channel MOSFET connected in series between a first potential and a second potential;
- said circuit block is set to the first operating condition depending on transfer of said control signal and to the second operating condition depending on the end of use of said circuit block;
- first current flows into the serially connected source-drain path of said complimentary MOSFET when the gate-source voltage of said first P-channel MOSFET or said first N-channel MOSFET is set to 0V in said first operating condition;
- and
- second current lower than said first current flows into the serially connected source-drain path of said complimentary MOSFET when the gate-source voltage of said first P-channel MOSFET or said first N-channel MOSFET is set to 0V in said second operating condition.
Dependencies are inferred from the claim text.