US 6,604,192 B1Granted

System and method for utilizing instruction attributes to detect data hazards

AssigneeHewlett-Packard Development Company, L.P.

InventorsRonny Lee Arnold, Donald Charles Soltis, Jr.

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Abstract

A computer system utilizing a processing system capable of efficiently comparing register identifiers and instruction attribute data to detect data hazards between instructions of a computer program is used to execute the computer program. The processing system utilizes at least one pipeline, a first decoder, a second decoder, and comparison logic. The pipeline receives and simultaneously processes instructions of a computer program. The first and second decoders are coupled to the pipeline and decode register identifiers associated with instructions being processed by the pipeline. The comparison logic is interfaced with the first and second decoders and receives the decoded register identifiers along with attribute data indicating the status and/or type of instructions being processed by the pipeline. The comparison logic compares the decoded register identifiers and the attribute data to other decoded register identifiers and attribute data to detect data hazards.

Claims29

Dependent claims

A computer system for processing instructions of a computer program, comprising:

a pipeline configured to simultaneously process a first instruction in a first stage of said pipeline and a second instruction in a second stage of said pipeline, said first stage configured to transmit a first set of attribute data associated with said first instruction and to transmit a first encoded register identifier associated with said first instruction, said second stage configured to transmit a second set of attribute data associated with said second instruction and to transmit a second encoded register identifier associated with said second instruction;
a first decoder coupled to said first stage and configured to receive said first encoded register identifier, said first decoder configured to decode said first encoded register identifier into a first decoded register identifier and to transit said first decoded register identifier;
a second decoder coupled to said second stage and configured to receive said second encoded register identifier, said second decoder configured to decode said second encoded register identifier into a second decoded register identifier and to transmit said second decoded register identifier;
comparison logic interfaced with said first and second decoders, said comparison logic configured to receive said first and second decoded register identifiers and to receive said first and second sets of attribute data, said comparison logic configured to detect a data hazard based on said first and second decoded register identifiers and based on said first and second sets of attribute data;
a first attribute interface coupled to said first decoder and said comparison logic, said first attribute interface configured to receive said first decoded register identifier and said first set of attribute data and to combine said first set of attribute data with said first decoded register identifier;
and
a second attribute interface coupled to said second decoder and said comparison logic, said second attribute interface configured to receive said second decoded register identifier and said second set of attribute data and to combine said second set of attribute data with said second decoded register identifier.

4 more elements

A computer system for processing instructions of a computer program, comprising:

a pipeline configured to simultaneously process a first instruction in a first stage of said pipeline and a second instruction in a second stage of said pipeline, said first stage configured to transmit a first set of attribute data associated with said first instruction and to transmit a first encoded register identifier associated with said first instruction, said second stage configured to transmit a second set of attribute data associated with said second instruction and to transit a second encoded register identifier associated with said second instruction;
a first decoder coupled to said first stage and configured to receive said first encoded register identifier, said first decoder configured to decode said first encoded register identifier into a first decoded register identifier and to transmit said first decoded register identifier, wherein said first decoder includes rows of decode logic respectively corresponding to a plurality of registers, each of said rows of decode logic configured to produce an output bit, said each row of decode logic configured to receive said first encoded register identifier and to assert said output bit when said first encoded register identifier identifies one of said registers corresponding to said each row, said each row of decode logic further configured to deassert said output bit when said first encoded register identifier identifies another one of said registers;
a second decoder coupled to said second stage and configured to receive said second encoded register identifier, said second decoder configured to decode said second encoded register identifier into a second decoded register identifier and to transmit said second decoded register identifier;
comparison logic interfaced with said fist and second decoders, said comparison logic configured to receive said first and second decoded register identifiers and to receive said first and second sets of attribute data, said comparison logic configured to detect a data hazard based on said first and second decoded register identifiers and based on said fist and second sets of attribute data;
and
an attribute interface having rows of interface logic, each of said rows of interface logic configured to receive said output bit firm one of said rows of decode logic and to receive said first set of attribute data, said interface logic configured to combine said output bit from said one of said rows of decode logic with said attribute data.

3 more elements

A method for processing instructions of a computer program, comprising the steps of:

transmitting an instruction to a pipeline of a processing system;
decoding an encoded register identifier associated with said instruction into a first decoded register identifier while said instruction is being processed by a first portion of said pipeline;
decoding said encoded register identifier into a second decoded register identifier while said instruction is being processed by a second portion of said pipeline;
transmitting a first set of attribute data associated with said instruction;
transmitting a second set of attribute data associated with said instruction;
comparing said first decoded register identifier and said first set of attribute data to decoded register identifiers and attribute data associated with other instructions;
comparing said second decoded register identifier and said second set of attribute data to decoded register identifiers and attribute data associated with other instructions;
detecting data dependency hazards based on said comparing steps;
combining said first set of attribute data with said first decoded register identifier;
and
combining said second set of attribute data with said second decoded register identifier.

8 more elements

A system for processing instructions of a computer program, comprising:

a pipeline configured to process a first instruction in a first stage of said pipeline, said first instruction associated with a first encoded register identifier;
a first decoder configured to receive said first encoded register identifier from said first stage and to decode said first encoded register identifier into a first decoded register identifier;
a first attribute interface configured to receive said first decoded register identifier and a first set of attribute data associated with said first instruction, said first attribute interface configured to combine said first decoded register identifier and said first set of attribute data thereby forming a first combined set of data, wherein said first attribute interface, when combining said first decoded register identifier and said first set of attribute data, is configured to coalesce at least one bit of said first decoded register identifier and at least one bit of said first set of attribute data into a coalesced bit of said first combined set of data;
and
comparison logic configured to detect a data hazard between said first instruction and another instruction based on said first combined set of data.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/490,389Filed 24 Jan 2000
Granted: 5 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/3867
Concurrent instruction execution, e.g. pipeline or look ahead: using instruction pipelines
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/3858
Instruction completion, e.g. retiring, committing or graduating: result writeback, i.e. updating the architectural state or memory
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling