Method and apparatus for accelerating instruction fetching for a processor

A data processing system for delivering instructions to a processor comprising:

• an instruction fetching unit (IFU);
• a sum-addressed instruction cache (I-cache) coupled to said IFU, said I-cache having a cache array and a plurality of line buffers with capacity for holding a line of multiple instructions, including a PRED buffer utilized to produce in-line instructions to an instruction buffer, a NEXT buffer utilized to allow a state machine to find idle cache bandwidth to pre-fetch a next cache line prior to a completion of the line of instructions in the PRED buffer, and an ALT buffer utilized for fetching targets of branch instructions;
• means for fetching said instructions from said I-cache to provide both target and in-line path;
• means for late selecting between target and in-line path instructions;
• means for delivering a full line of said cache array to one of said buffers in two cycles;
• and
• means for providing up to four instructions aligned to an instruction boundary to an instruction buffer.

An instruction fetching mechanism of a processor comprising:

• an instruction fetching unit (IFU);
• an instruction cache (I-cache) coupled to said IFU, wherein said I-cache includes:
• sum address buffers which provide said I-cache with a line address based on two address operands received from said IFU;
• a 64 byte cache array, having a plurality of instruction lines with a capacity for 32 instructions per line;
• an array formatter for providing a target instruction directly from said cache array to an instruction buffer during branch processing;
• a PRED buffer, which holds a line of instructions presently being completed;
• a PRED formatter for providing up to four in-line instructions to said instruction buffer;
• an ALT buffer, which holds the target line of instructions, wherein said target line of instructions is fetched prior to a resolution of a corresponding branch instruction in the instruction buffer;
• and
• a NEXT buffer, which holds the next line of instructions required until a present line of instructions in the PRED buffer is completed.