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US 6,604,189 B1Granted
Master/slave processor memory inter accessability in an integrated embedded system
AssigneeLSI Logic Corporation
InventorsBoris Zemlyak, Ariel Cohen
Life of this patent
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AssigneeLSI Logic Corporation
InventorsBoris Zemlyak, Ariel Cohen
Estimating the term…
An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.
An apparatus comprising:
An apparatus comprising:
A method for implementing interaccessable processors, comprising the steps of:
Dependencies are inferred from the claim text.