Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction

A VLIW processor for processing instructions, comprising:

• a source of VLIW instructions, at least some of said VLIW instructions comprising a plurality of individual atom instructions defining distinct operations;
• a plurality of distinct functional execution units, each of said functional units for executing different operations, whereby individual atoms within a VLIW instruction may be executed in parallel;
• an instruction pipeline, said instruction pipeline including multiple stages, and said multiple stages including an execution stage;
• a source of control information for each VLIW instruction, said control information pertaining to each individual atom instruction contained within said VLIW instruction;
• a control information pipeline, said control information pipeline including multiple stages;
• a pipeline control unit for asserting VLIW instructions into said pipeline and for concurrently inputting said control information for said atom instructions within said VLIW instruction into said control information pipeline;
• said instruction pipeline and said control information pipeline being operated in synchronism with one another to advance said control information through said multiple stages of said control pipeline in synchronism with advancement of said VLIW instruction through said multiple stages of said instruction pipeline to link said control information to said individual atoms of said VLIW instruction, and wherein said instruction pipeline is configured to flush all VLIW instructions upon detection of a multi-cycle atom operation within said VLIW instruction.

A VLIW processor for processing instructions, comprising:

• a source of VLIW instructions, at least some of said VLIW instructions comprising a plurality of individual atom instructions defining distinct operations;
• a plurality of distinct functional execution units, each of said functional units for executing different operations, whereby individual atoms within a VLIW instruction may be executed in parallel, said plurality of functional execution units including:
• a memory unit and a floating point unit;
• an instruction pipeline, said instruction pipeline including multiple stages, and said multiple stages including an execution stage;
• an address pipeline, said address pipeline including multiple stages;
• a source of control information for each VLIW instruction, said control information pertaining to each individual atom instruction contained within said VLIW instruction, said control information comprising a plurality of bits, each of said bits being associated with a respective one of said individual functional execution units and all of said bits being associated with the pipeline control unit and wherein each of said bits may be set ENABLED or set DISABLED;
• a control information pipeline, said control information pipeline including multiple stages;
• a pipeline control unit for asserting VLIW instructions into said pipeline and for concurrently inputting said control information for said atom instructions within said VLIW instruction into said control information pipeline and said VLIW instruction address in said address pipeline;
• said instruction pipeline, said address pipeline and said control information pipeline being operated in synchronism with one another to advance said control information through said multiple stages of said control pipeline in synchronism with advancement of said VLIW instruction through said multiple stages of said instruction pipeline to link said control information to said individual atoms of said VLIW instruction;
• said pipeline control unit including means for retrieving the address of said VLIW instruction from said address pipeline, responsive to a kill signal produced by a functional execution unit;
• at least said memory unit and said floating point unit of said plurality of functional execution units and said pipeline control unit including:
• checking means for checking and interpreting the setting of a respective one of said plurality of bits;
• said functional execution units for performing the second part of a multi-cycle operation of an atom presented for execution and for preventing reissue of a kill signal and a multi-cycle request signal, when said checking means of said functional execution units interprets said bit as ENABLED;
• said functional execution units including:
• means for determining whether an atom is for a multi-cycle operation;
• means, responsive to a determination that an atom is for a multi-cycle operation, for producing a kill signal, wherein said instruction pipeline is cleared of all VLIW instructions, and for producing and sending a stall signal to said pipeline control unit, and for producing a multi-cycle request signal;
• and
• means, responsive to an authorization signal from said pipeline control unit, for performing the first part of a multi-cycle operation of a multi-cycle atom present for execution;
• and
• wherein said pipeline control unit includes:
• means for detecting a stall signal to pause said pipeline when said pipeline has been cleared of all VLIW instructions, excepting a plurality of VLIW instructions pending at said functional execution units, and for detecting a multi-cycle request signal from a functional execution unit, and, responsive to said multi-cycle request signal from a functional execution unit, for sending, in the absence of occurrence of an exception or interrupt signal, an authorization signal to the functional execution unit that sent said multi-cycle signal to permit said functional execution unit to execute said first part of said multi-cycle operation;
• said pipeline control unit for setting the respective bit associated with said multi-cycle atom within said control information to ENABLE to provide revised control information, whereby the second part of a multi-cycle operation is indicated, for reasserting said VLIW instruction in said instruction pipeline, following sending of said authorization signal, and for asserting said revised control information in said control information pipeline concurrently with said reassertion of said VLIW instruction.

A VLIW computer, comprising:

• an instruction pipeline;
• an address pipeline;
• a control information pipeline;
• a pipeline control unit for asserting VLIW instructions into said pipeline, and, concurrently, asserting said VLIW instruction address into said address pipeline, and asserting control information into said control information pipeline;
• said VLIW instructions including multiple atoms defining different individual operations, one of said individual operations sometimes comprising an operation that requires multiple cycles of a functional unit to complete defining a multi-cycle atom;
• said pipeline control unit for controlling each of said instruction pipeline, said address pipeline and said control information pipeline and producing inter-stage transfer of a plurality of bits in said pipelines in synchronism with one another;
• said control information pipeline comprising multiple stages whereby control information asserted into said control pipeline is transferred through serial stages, stage by stage, under control of said pipeline control unit;
• said address pipeline containing multiple stages whereby address information asserted into said address pipeline is transferred through serial stages, stage by stage, under control of said pipeline control unit;
• a plurality of functional units for executing atoms when presented at the execution stage of said instruction pipeline;
• at least a portion of said plurality of functional units being capable of determining whether an atom presented thereto constitutes a multi-cycle operation;
• said portion of functional units including:
• means for determining whether an atom is a multi-cycle atom;
• means for testing said control information pipeline for an indication of control information identifying a second part to a multi-cycle operation;
• said functional unit for executing said atom, responsive to determining that said atom does not constitute a multi-cycle atom, and for generating a multi-cycle detect signal, issuing a kill signal to clear said instruction pipeline of all instructions and halt all other of said functional execution units, when said atom is identified as a multi-cycle atom;
• said functional unit communicating said multi-cycle detect signal to said pipeline control unit, whereby said pipeline control unit recognizes a determination of a multi-cycle atom;
• said pipeline control unit for retrieving said address of said VLIW instruction from said address pipeline and storing said VLIW instruction address, responsive to said multi-cycle detect signal;
• said pipeline control unit further determining occurrence of any exception or interrupt signals, responsive to said “multi-cycle detect signal”;
• said pipeline control unit, responsive to non-occurrence of an exception or interrupt signal, for authorizing said functional unit responsible for said multi-cycle detect signal to execute said multi-cycle atom, whereby said first part of said multiple, cycle operation is completed;
• said pipeline control unit further including:
• means for reasserting said VLIW instruction containing said multi-cycle atom responsible for said multi-cycle detect signal into said pipeline, including, upon said reassertion, marking said control information associated with said multi-cycle atom to indicate the second part of the multiple cycle operation and asserting said control information in said control information pipeline, concurrently with reassertion of said VLIW instruction;
• said functional unit responsible for said multi-cycle detect signal, being responsive to detection of the presence for execution of the second part of a multi-cycle atom, for executing the second part of said multiple cycle operation and preventing reassertion of a multi-cycle detect signal.