Distribution of address-translation-purge requests to multiple processors
AssigneeSilicon Graphics, Inc.
InventorEric C. Fromm
Life of this patent
Estimating the term…
Abstract
A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.
Claims16
A computer system, comprising:
- a node controller comprising sequencing logic, wherein the sequencing logic receives a write command from a network, translates the write command into a Purge Translation Cache (PTC) instruction, and sends the PTC instruction to a bus;
- and
- a processor connected to the node controller via the bus, wherein the processor comprises:
- a translation lookaside buffer, and
- bus control logic, wherein the bus control logic receives the PTC instruction and
- purges a virtual address specified in the PTC instruction from the translation lookaside buffer wherein the node controller further comprises a memory mapped register (MMR) and the write command is a MMR write command.
A multi-processor, shared-memory system, comprising:
- a first processor, wherein the first processor sends a write command across a first bus;
- a first node controller comprising first sequencing logic, wherein the first sequencing logic receives the write command from the first bus and sends the write command across a network;
- a second node controller comprising second sequencing logic, wherein the second sequencing logic receives the write command from the network, translates the write command into a Purge Translation Cache (PTC) instruction, and sends the PTC instruction across a second bus;
- and
- a second processor connected to the second node controller via the second bus, wherein the second processor comprises:
- a translation lookaside buffer, and
- bus control logic, wherein the bus control logic receives the PTC instruction and
- purges a virtual address specified in the PTC instruction from the translation lookaside buffer wherein the second node controller further comprises a memory mapped register (MMR) and the write command is a MMR write command.
A method for deallocating memory, comprising:
- receiving a write command from a network;
- translating the write command into a Purge Translation Cache (PTC) instruction;
- sending the PTC instruction across a bus to a processor;
- receiving the PTC instruction at the processor;
- and
- purging a virtual address specified in the PTC instruction from a translation lookaside buffer wherein the write command is a memory mapped register (MMR) write command.
A computer system, comprising:
- a node controller comprising sequencing logic, wherein the sequencing logic receives a plurality of write commands from a network, translates the plurality of write commands into a plurality of Purge Translation Cache (PTC) instructions, and sends the plurality of PTC instructions one at a time in series to a bus;
- and
- a processor connected to the node controller via the bus, wherein the processor comprises:
- a translation lookaside buffer, and
- bus control logic, wherein the bus control logic receives one of the plurality of PTC instructions and purges a virtual address specified in the PTC instruction from the translation lookaside buffer wherein the node controller further comprises a memory mapped register (MMR) and the plurality of write commands are MMR write commands.
Dependencies are inferred from the claim text.