Communication of dissimilar data between lock-stepped processors

A processing system, comprising:

• first and second processor units coupled for lockstep operation to execute identical instruction streams;
• a storage facility having at least first and second storage locations;
• a first instruction in the identical instruction streams to respectively cause each of the first and second processor units to write data to the first storage location;
• means for redirecting the data from the second processor unit to the second storage location;
• and
• a second instruction in the identical instruction streams to respectively cause each of the first and second processor units to read the first and second storage locations,
• whereby, the first and second processor units exchange data between them.

A processing system, comprising:

• first and second processor units operating in lockstep to execute substantially identical instruction streams, instruction by instruction;
• a main memory shared by the first and second processor units for storing and retrieving data words, each of the data words being protected by error correcting code;
• and
• error correcting circuitry operating to correct errors in data words accessed at the main memory,
• wherein the first and second processor units are coupled for exchanging information respecting error counts.

A method for exchanging data between two processors engaged in lockstep and compare operations, each of the two processors being associated with a status register, the method comprising:

• writing to a first address, by each of the two processors, contents of their associated status register, the first address used by a second of the two processors being redirected to render it different than the first address used by the first of the two processors;
• reading, by the two processors, data at the first address;
• writing to a second address, by each of the two processors, contents of their associated status register, the second address used by the first of the two processors being redirected to render it different than the second address used by the second of the two processors;
• and
• reading, by the two processors, data at the second address, whereby the two processors are able to exchange dissimilar data without having to diverge from their instruction stream.