Data storage system having plural fault domains

A memory system, comprising:

• (A) a memory array region for storing information, such memory array region having:
• (a) a DATA port;
• (b) a pair of memory control ports;
• (B) a pair of logic sections, each one thereof having:
• (a) a logic section control port connected to a corresponding one of the pair of memory control ports for providing memory control signals to the memory array region, and,
• (b) a logic section DATA port, and
• (c)wherein the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port;
• (C) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic sections to provide clock signals to such one of the logic sections.

A memory system, comprising:

• (A) a memory array region for storing information, such memory array region having:
• (a) a DATA port for receiving the write data to be written into such region and for providing read data read from such region, such writing of such write data and reading of such read data being in response to control signals fed to such memory region;
• (b) a pair of memory control ports, each one for receiving the control signals;
• (B) a pair of logic sections, each one thereof having:
• (a) a pair of upper ports;
• (b) a logic section control port connected to a corresponding one of the pair of memory control ports;
• and,
• (c) a logic section DATA port;
• and
• (C) wherein:
• the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port;
• and
• each one of the pair of logic sections is adapted to provide data to, and receive data from, the DATA port of the memory array region via the DATA port of such one of the logic sections in response to clock signals fed thereto when such one of the logic sections is granted access to the memory array DATA port as a result of an arbitration between such pair of logic section, such data being provided or received in response to the control signals produced by such one of the logic sections at the control port thereof;
• and
• (D) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic section to provide to such one of the logic sections the clock signals therefor.

An interface for coupling a plurality of processors, such processors being arranged in pairs, each one of the processors in such pair being coupled to a common interface port, such interface, comprising:

• (A) a memory section;
• such memory section having:
• a pair of memory section ports;
• a memory array region;
• and,
• a switching section, such switching section being coupled between the pair of memory section ports and the memory array region;
• (B) a director for coupling between the common interface port and the pair of memory ports;
• (C) wherein the memory array stores information, such memory array region having:
• (a) a DATA port;
• (b) a pair of memory control ports;
• (D) wherein such switch section comprises:
• (a) a pair of logic sections, each one thereof having:
• (i) a logic section control port connected to a corresponding one of the pair of memory control ports for providing memory control signals to the memory array region, and,
• (ii) a logic section DATA port, and
• (iii) wherein the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port;
• (b) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic sections to provide clock signals to such one of the logic sections.

An interface for coupling a plurality of processors, such processors being arranged in pairs, each one of the processors in such pair being coupled to a common interface port, such interface, comprising:

• (A) a memory section;
• such memory section having:
• a pair of memory section ports;
• a memory array region;
• and,
• a switching section, such switching section being coupled between the pair of memory section ports and the memory array region;
• (B) a director for coupling between the common interface port and the pair of memory ports;
• (C) wherein the memory array stores information, such memory array region having:
• (a) a DATA port for receiving the write data to be written into such region and for providing read data read from such region, such writing of such write data and reading of such read data being in response to control signals fed to such memory region;
• (b) a pair of memory control ports, each one for receiving the control signals;
• (D) wherein the switching section comprises:
• (a) a pair of logic sections, each one thereof having:
• (i) a pair of upper ports;
• (ii) a logic section control port connected to a corresponding one of the pair of memory control ports;
• and,
• (iii) a logic section DATA port;
• and
• (b) wherein:
• the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port;
• and
• each one of the pair of logic sections is adapted to provide data to, and receive data from, the DATA port of the memory array region via the DATA port of such one of the logic sections in response to clock signals fed thereto when such one of the logic sections is granted access to the memory array DATA port as a result of an arbitration between such pair of logic section, such data being provided or received in response to the control signals produced by such one of the logic sections at the control port thereof;
• and
• (c) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic section to provide to such one of the logic sections the clock signals therefor.

A memory board, comprising:

• (A) a plurality of memory array regions, each one of such regions having a common DATA port and a pair of independent memory array control ports;
• (B) a plurality of logic sections, each one of the logic sections having:
• a first logic section upper port, a second logic section upper port, a logic section control port, and a logic section DATA port;
• wherein:
• such plurality of logic sections are arranged in pairs, each pair being coupled to a corresponding one of the plurality of array regions;
• a logic section in each pair thereof having:
• the DATA port of such pair of logic sections connected to the memory DATA port of the corresponding one of the memory array region;
• the control port thereof connected to a corresponding one of the pair of memory array control ports the corresponding one of the memory array regions;
• (C) a plurality of crossbar switches, each one thereof having a plurality of crossbar switch upper ports and a plurality of crossbar switch lower ports, such crossbar switch upper ports and crossbar switch lower ports being coupled in accordance with information fed to the crossbar switch upper ports,
• wherein a first one of the crossbar switches has each one of the crossbar switch lower ports thereof connected to the first logic section upper port of a first one of the logic sections in a corresponding one of the pairs of such logic sections
• wherein a second one of the crossbar switches has each one of the crossbar switch lower ports thereof connected to the second logic section upper port of the first one of the logic sections in a corresponding one of the pairs of such logic sections;
• wherein a third one of the crossbar switches has each one of the crossbar switch lower ports thereof connected to the first logic section upper port in a second one of the logic sections in a corresponding one of the pairs of such logic sections;
• wherein a fourth one of the crossbar switches has each one of the crossbar switch lower ports thereof connected to the second one of the pair of logic section upper ports of a corresponding one of the second logic sections in a corresponding one of the pairs of such logic sections;
• a pair of independent clocks, a first one of such clocks being fed to the first and second ones of the crossbar switches and to the first one of the logic sections in each one of the pair thereof, a second one of such clocks being fed to the third and fourth ones of the crossbar switches and to the second one of the logic sections in each one of the pair thereof.