US 6,604,174 B1Granted

Performance based system and method for dynamic allocation of a unified multiport cache

AssigneeInternational Business Machines Corporation

InventorsAlvar A. Dean, Kenneth J. Goodnow, Stephen W. Mahin, Wilbur D. Pricer, Dana J. Thygesen, Sebastian T. Ventrone

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Abstract

The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport cache. Therefore, multiple processes, which could be processors, tasks, or threads can access the cache during any cycle. Moreover, the ways of the cache can be allocated to the different processes and then dynamically reallocated based on performance. Most preferably, a relational cache miss percentage is used to reallocate the ways, but other metrics may also be used.

Claims16

Dependent claims

A multiport cache system comprising:

a cache having a plurality of ways each having a plurality of lines, each line having a plurality of data locations;
a tag having a plurality of tag entries, each tag entry corresponding to one of the data locations, each tag entry having an identification indicating which one of a plurality of processes is assigned to a corresponding one of the data locations;
and
a memory controller having:
a Tag Allocation Controller (TAC) dynamically allocating the plurality of processes to the plurality of ways, the TAC reallocating the plurality of processes to the plurality of ways based on periodic evaluations of system performance;
and
a way assignment memory having entries each defining which way is assigned to which process;
a processes-to-cache multiplexor, coupled to a plurality of buses and to write ports of the cache, having a plurality of multiplexors each having input coupled to the buses and one output coupled to one of the write ports of the cache;
and
a cache-to-processes multiplexor, coupled to a plurality of buses to read ports of the cache, having a plurality of multiplexors each having inputs coupled to the buses and one output coupled to one of the read ports of the cache.

7 more elements

A method comprising the steps of:

providing a multiport cache having a plurality of ways and able to be accessed by a plurality of processes;
evaluating system performance periodically for one cache miss number per process, each of the cache miss numbers having a number of misses for one of the plurality of processes;
determining a total number of misses by adding all of the cache miss numbers during the system evaluation;
determining if the total number of misses is greater than a cache miss percentage;
and
reallocating the plurality of processes to the plurality of ways of the multiport cache based on the number of cache misses that are greater than the cache miss percentage.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/709,872Filed 10 Nov 2000
Granted: 5 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0853
Multiple simultaneous or quasi-simultaneous cache accessing: cache with multiport tag or data arrays
G06F 12/0844
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: multiple…
G06F 12/0846
Multiple simultaneous or quasi-simultaneous cache accessing: cache with multiple tag or data arrays being simultaneously accessible
G06F 2212/502
Control mechanisms for virtual memory, cache or TLB: using adaptive policy