US 6,604,163 B1Granted

Interconnection of digital signal processor with program memory and external devices using a shared bus interface

AssigneeKoninklijke Philips Electronics N.V.

InventorJean Francois Duboc

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Abstract

A circuit arrangement and method reduce the number of interconnects required for a digital signal processor by utilizing a shared bus to interconnect the digital signal processor to both a program memory and at least one external device. An instruction cache is utilized to cache selected instructions from a DSP program such that, whenever a cached copy of a DSP program instruction is available in the instruction cache, the cached copy can be fetched from the instruction cache instead of the program memory, thereby freeing the shared bus for performing an access to the external device. Caching of instructions and subsequent freeing of the shared bus for external device access may be conditioned on detection of a loop, whereby instructions from the loop are cached in the instruction cache and fetched during subsequent passes through the loop.

Claims17

Dependent claims

A circuit arrangement for use in executing a digital signal processor (DSP) program to process digital signal data, the circuit arrangement comprising:

(a) a data bus interface configured to interface with a data memory over a data bus so as to communicate digital signal data with the data memory;
(b) a shared bus interface configured to interface with a program memory and an external device over a shared bus having an address bus and a data bus so as to communicate instructions from a DSP program with the program memory, and to communicate external device data with the external device;
(c) an instruction cache configured to cache at least one instruction from the DSP program;
(d) a digital signal processor coupled to the data bus interface, the shared bus interface, and the instruction cache, the digital signal processor configured to concurrently retrieve an instruction from the DSP program from the instruction cache, communicate with the data memory over the data bus interface, and communicate with the external device over the shared bus interface;
(e) wherein the digital signal processor includes:
(1) an instruction decoder configured to decode instructions from the DSP program;
(2) a program control unit coupled to the instruction decoder and configured to generate instruction address requests for instructions from the DSP program;
(3) an address generator coupled to the instruction decoder and configured to generate external device address requests for accessing the external device;
and
(4) a bus control unit coupled to the instruction decoder and configured to select one of a program memory access mode and an external device access mode for the shared bus;
and
(f) wherein the shared bus interface includes:
(1) a first multiplexer coupled to the bus control unit and configured to couple the program control unit to the address bus from the shared bus when the program memory access mode is selected, and to couple the address generator to the address bus from the shared bus when the external device access mode is selected;
and
(2) a second multiplexer coupled to the bus control unit and configured to couple the data bus from the shared bus to the instruction decoder when the program memory access mode is selected, and to couple the instruction cache to the instruction decoder when the external device access mode is selected.

12 more elements

A method of processing digital signal data with a digital signal processing (DSP) circuit arrangement, the method comprising:

(a) executing instructions form a DSP program stored in a program memory coupled to a shared bus interface, the shared bus interface further coupled to an external device interface that interfaces an external device with the shared bus interface;
(b) caching at least one instruction form the DSP program in an instruction cache;
(c) concurrently retrieving an instruction from the DSP program from the instruction cache, communicating with a data memory over a data bus interface, and communicating with the external device over the shared bus interface;
and
(d) wherein concurrently retrieving an instruction from the DSP program from the instruction cache, communicating with a data memory over a data bus interface, and communicating with the external device over the shared bus interface comprises:
generating with a program control unit an instruction address request for the instruction;
generating with an address generator an external device address request for accessing the external device;
routing the external device address request to the external device over the shared bus interface;
routing the instruction address request to the instruction cache;
and
routing a cached copy of the instruction to an instruction decoder.

8 more elements

Dependencies are inferred from the claim text.