Snoop stall reduction on a microprocessor external bus
AssigneeIntel Corporation
InventorsLokpraveen B. Mosur, Subramaniam Maiyuran
Life of this patent
Estimating the term…
Abstract
A method and apparatus for reducing snoop stall on an external bus. One method of the present invention comprises retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of the bus transaction. Then it is determined whether the bus transaction is a snoopable memory transaction or not. If the bus transaction is a snoopable memory transaction, a snoop probe is dispatched during the first request phase packet of the transaction. Snooping devices are allowed additional bus clocks to respond to the snoop probe, thereby reducing the number of snoop stalls required to be inserted during the bus transaction.
Claims46
A method comprising:
- retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of said bus transaction;
- determining whether said bus transaction is a snoopable memory transaction;
- and
- dispatching a snoop probe during said first request phase packets if said bus transaction is a snoopable memory transaction.
An apparatus comprising:
- snoop logic coupled to an external processor bus, said snoop logic to issue a snoop probe during a first of a plurality of request phase packets of a snoopable memory transaction;
- a first snoopable internal unit coupled to said snoop logic, said first snoopable internal unit to receive said snoop probe.
An integrated circuit device comprising:
- a bus interface coupled to an external processor bus;
- an external request queue coupled to said bus, said external request queue to drive a transaction address onto said bus;
- snoop logic coupled to said bus, said snoop logic to issue a snoop probe during a first of a plurality of request phase packets of a snoopable memory transaction;
- and
- a first snoopable internal unit coupled to said snoop logic, said first snoopable internal unit to receive said snoop probe.
A system comprising:
- a first caching agent coupled to a bus, said first caching agent to initiate a snoopable memory transaction on said bus;
- a second caching agent couple to said bus, said second caching agent comprising:
- snoop logic coupled to said bus, said snoop logic to issue a snoop probe during a first of a plurality of request phase packets of said snoopable memory transaction;
- and
- a first snoopable internal unit coupled to said snoop logic, said first snoopable internal unit to receive said snoop probe.
A method comprising:
- detecting an address strobe during a request phase for an external bus transaction, wherein in response to said address strobe, a transaction address in a first of a plurality of request packets of said request phase is acquired;
- determining whether a self snoop attribute is associated with said first request packet;
- and
- initiating a snoop of a internal memory.
An apparatus comprising:
- snoop logic to detect an address strobe during communication of a first of a plurality of request packets for a request phase of a bus transaction, wherein said snoop logic in response to detection of said address strobe is to acquire a transaction address from said first request packet;
- and
- a snoop queue coupled to said snoop logic, said snoop queue to dispatch a snoop probe to a memory internal to said apparatus if a self snoop signal is detected as being associated with said first request packet.
A system comprising:
- a first caching agent coupled to a bus, said first caching agent to receive a transaction on said bus;
- and
- a second caching agent couple to said bus, said second caching agent to initiate and snoop transactions on said bus, said second caching agent comprising:
- snoop logic to detect an address strobe during communication of a first of a plurality of request packets for a request phase of a bus transaction, wherein said snoop logic in response to detection of said address strobe is to acquire a transaction address from said first request packet;
- and
- a snoop queue coupled to said snoop logic, said snoop queue to dispatch a snoop probe to a memory internal to said second caching agent if a self snoop signal is detected as being associated with said first request packet.
Dependencies are inferred from the claim text.