Translation of PCI level interrupts into packet based messages for edge event drive microprocessors

A computer system comprising:

• one or more Peripheral Component Interconnect (PCI) devices for generating interrupts;
• an interrupt line for conveying the interrupts generated by the PCI devices;
• a bridge device, coupled to the interrupt line, for receiving the interrupts from the PCI devices via the interrupt line, wherein, when the bridge device receives the interrupts, the bridge device generates an interrupt write packet;
• one or more microprocessors communicatively coupled to the bridge device, wherein the one or more microprocessors includes a first microprocessor, wherein the first microprocessor receives the interrupt write packet from the bridge device and initiates an interrupt routine;
• and
• a PCI bus coupled to the bridge device for receiving write transactions generated by the PCI devices, wherein, when the bridge device receives the write transactions, the bridge device checks the write transactions for error and flags the write transactions having an error, wherein the bridge device further translates the write transactions error into one or more write request packets.

A computer system comprising:

• one or more Peripheral Component Interconnect (PCI) devices for generating interrupts;
• an interrupt line for conveying the interrupts generated by the PCI devices;
• a bridge device, coupled to the interrupt line, for receiving the interrupts from the PCI devices via the interrupt line, wherein, when the bridge device receives the interrupts, the bridge device generates an interrupt write packet;
• one or more microprocessors communicatively coupled to the bridge device, wherein the one or more microprocessors includes a first microprocessor, wherein the first microprocessor receives the interrupt write packet from the bridge device and initiates an interrupt routine;
• and
• wherein the computer system further comprises a PCI bus connected to the bridge device and to the PCI devices, wherein the bridge device comprises a PCI slave, coupled to the PCI bus, for checking parity errors in write transactions received from the PCI device.

A method of processing interrupts received from PCI devices, the method comprising:

• receiving an interrupt;
• constructing an interrupt write packet, wherein the interrupt write packet includes a PCI device identifier and a destination address;
• transmitting the interrupt write packet to a CPU;
• receiving the interrupt write packet at the CPU;
• starting an interrupt routine associated with interrupt;
• generating a non-blocking write;
• checking whether the interrupt is still active;
• and
• if the interrupt is still active, generating a new interrupt write packet to the CPU.