Data release to reduce latency in on-chip system bus

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable medium having computer readable program code embodied in said medium for causing an on-chip computing bus to be developed, said computer readable program code comprising:
• first computer readable program code for providing a bus interface, for coupling a processing device to the on-chip computing bus;
• and
• second computer readable program code for providing data release drive and control logic that is coupled to said bus interface, that presents a data release signal to the on-chip computing bus during the last cycle of a data transfer, wherein said data release drive and control logic monitors the on-chip computing bus for a data release signal driven by other on-chip processing devices.

A method for granting access to a data bus within an on-chip multi-master environment, the method comprising:

• when the data bus is being accessed by a first master device, providing a data bus grant signal to a second master device;
• before the first master device relinquishes access to the data bus, driving a data bus release signal from the first master device to the second master device;
• and
• accessing the data bus by the second master device, after it receives the data bus release signal from the first master device;
• wherein the data bus is accessed by the first master device for an indeterminate number of bus cycles.