US 6,604,116 B1Granted

Decreasing memory return latency by predicting the order of completion of partially ready returns

AssigneeHewlett-Packard Development Company, L.P.

InventorChandrasekaran Nagesh Gupta

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Abstract

The inventive memory controller reduces the latency of memory data returns for memory read request transactions. The memory controller is connected between at least one bus and a memory, with the bus connected to at least two processors. The memory controller examines a storage queue that stores information on the phase status of the transactions to determine whether completed transactions exist, and if not, to predict which partially completed transaction is most likely to become completed next. The memory controller returns the data for completed transactions and sets up the data return for the partially completed transaction that is most likely to become completed next. Multiple read requests may be processed out of order to maximize the memory bus utilization and throughput.

Claims20

Dependent claims

A memory controller for managing memory transactions from a plurality of processors, wherein the memory controller is connected between a memory and at least one bus, the plurality of processors are connected to the one bus, and each transaction originated from a particular processor of the plurality of processors, the memory controller comprising:

a storage queue for storing status information of the memory transactions from the one bus;
and
a state machine for determining whether any of the transactions are completed transactions based on the status information, and if there are no completed transactions, determines which of the transactions is a partially completed transaction that is most likely to become a completed transaction based on the status information;
wherein if there is at least one completed transaction, then the memory controller forms a response and returns the response to the originating processor;
and
if there are no completed transactions, the memory controller sets up a response for the partially completed transaction and holds the response until the partially completed transaction becomes a completed transaction.

3 more elements

A method for managing memory transactions from a plurality of processors with a memory controller, wherein the memory controller is connected between a memory and at least one bus, the plurality of processors are connected to the one bus, and each transaction originated from a particular processor of the plurality of processors, the method comprising the steps of:

storing status information of the memory transactions from the one bus in a storage queue;
determining whether any of the transactions are completed transactions based on the status information, via a state machine;
determining, if there are no completed transactions, which of the transactions is a partially completed transaction that is most likely to become a completed transaction based on the status information, via the state machine;
forming a response, if there is at least one completed transaction, for the one completed transaction, and returning the response to the originating processor;
and
setting up a response, if there are no completed transactions, for the partially completed transaction, and holding the response until the partially completed transaction becomes a completed transaction.

3 more elements

Dependencies are inferred from the claim text.