Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library

A storage element storing a computer readable program for calculating a delay in signal propagation time for a logic circuit composed of a plurality of circuit blocks resulting from different effective power-source voltages at which said circuit blocks operate, each of said circuit blocks being composed of a plurality of logic elements each including a FET, said program directing a computer to execute the steps of:

• calculating a power-source voltage coefficient which is a ratio of the power-source voltage for each of said circuit blocks to a reference power-source voltage;
• calculating a current coefficient which is a ratio of a drain saturation current in said FET when the reference power-source voltage is applied thereto to a drain saturation current in said FET when the effective power-source voltage for each of said circuit blocks is applied thereto;
• and
• calculating a reference delay time, the reference delay time being a delay time for each of said circuit blocks when said reference power-source voltage is applied thereto;
• calculating a product of said reference delay time, said power-source voltage coefficient for each of said circuit blocks, and said current coefficient for each of said circuit blocks;
• and
• designating the result of said product as an effective delay time which is a delay time for each of said circuit blocks.

A storage element storing a computer readable program for calculating a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for said logic circuit resulting from a variation in power-source voltage, said program directing a computer to execute the steps of:

• calculating a voltage variation caused by a current consumed by said logic circuit and by a wiring parasitic on a power-source line and calculating a difference between a reference power-source voltage applied to a power-source terminal and said voltage variation to calculate an effective power-source voltage applied to said logic circuit;
• calculating a power-source voltage coefficient which is a ratio of said effective power-source voltage to said reference power-source voltage, while calculating a current coefficient which is a ratio of a drain saturation current in said FET when said reference power-source voltage is applied thereto to a drain saturation current in said FET when said effective power-source voltage is applied thereto;
• and
• calculating a reference delay time, said reference delay time being a delay time for said logic circuit when said reference power-source voltage is applied thereto using said reference delay time data;
• calculating a product of said reference delay time, said power-source voltage coefficient for said logic circuit, and said current coefficient for said logic circuit;
• and
• determining the result of said product as an effective delay time which is a delay time for said logic circuit when said effective power-source voltage is applied thereto.