US 6,604,060 B1Granted

Method and apparatus for determining CC-NUMA intra-processor delays

AssigneeBull HN Information Systems Inc.

InventorsCharles P. Ryan, Eric E. Conway

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Abstract

In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors (92) sharing an L2 cache (94) differs from the time it takes for those signals to travel between processors (92) not sharing the same L2 cache (94). This difference, or DELTA, is dynamically computed by computing (332) the time it takes for a invalidate cache line cache command to travel between a local processor (92) and a master processor (92). This computation (334) is then made for the time it takes the signal to travel between a remote processor (92) and the master processor (92). The difference (336) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment (180).

Claims15

Dependent claims

In a data processing system having a plurality of processors, a method of dynamically calculating a difference between a time it takes a signal to travel between a first test processor and a second test processor and a time it takes a signal to travel between the first test processor and a third test processor, the first test processor being one of a first pair of test processors, the second test processor being one of the first pair of test processors, and the third test processor being one of a second pair of test processors,

said method comprising:
A) calculating a first delay time for the time it takes the signal to travel between the first test processor and the second test processor by:
1) providing a Synchronize signal to each of the first and second test processors;
2) waiting for the Synchronize signal by each of the first and second test processors;
3) providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in substep A)1);
4) signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both the first and second test processors complete the waiting in substep A)2);
5) recording the invalidating in substep A)4) in a trace entry in a trace in the first test processor;
and
6) finding the trace entry in the trace containing the invalidating in substep A)4);
B) calculating a second delay time for the time it takes the signal to travel between the first test processor and the third test processor by:
1) providing a Synchronize signal to each of the first and third test processors;
2) waiting for the Synchronize signal by each of the first and third test processors;
3) providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in substep B)1);
4) signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both of the test processors complete the waiting in substep B)2);
5) recording the invalidating in substep B)4) in a trace entry in a trace in the first test processor;
and
6) finding the trace entry in the trace containing the invalidating in substep B)4);
and
C) calculating the difference by subtracting the first delay time from the second delay time.

16 more elements

In a data processing system having a plurality of processors and containing software stored in a Computer Software Storage Medium for dynamically calculating a difference between a time it takes a signal to travel between a first test processor and a second test processor and a time it takes a signal to travel between the first test processor and a third test processor, the first test processor being one of a first pair of test processors, the second test processor being one of the first pair of test processors, and the third test processor being one of a second pair of test processors,

said software comprising:
A) a set of computer instructions stored in the Computer Software Storage Medium for calculating a first delay time for the time it takes the signal to travel between the first test processor and the second test processor comprising:
1) a subset of computer instructions for providing a Synchronize signal to each of the first and second test processors;
2) a subset of computer instructions for waiting for the Synchronize signal by each of the first and second test processors;
3) a subset of computer instructions for providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in subset A)1);
4) a subset of computer instructions for signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both of the test processors complete the waiting in subset A)2);
5) a subset of computer instructions for recording the invalidating in substep A)4) in a trace entry in a trace in the first test processor;
and
6) a subset of computer instructions for finding the trace entry in the trace containing the invalidating in subset A)4);
B) a set of computer instructions stored in the Computer Software Storage Medium for calculating a second delay time for the time it takes the signal to travel between the first test processor and the third test processor comprising:
1) a subset of computer instructions for providing a Synchronize signal to each of the first and third test processors;
2) a subset of computer instructions for waiting for the Synchronize signal by each of the first and third test processors;
3) a subset of computer instructions for providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in subset B)1);
4) a subset of computer instructions for signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both of the test processors complete the waiting in subset B)2);
5) a subset of computer instructions for recording the invalidating in substep B)4) in a trace entry in a trace in the first test processor;
and
6) a subset of computer instructions for finding the trace entry in the trace containing the invalidating in subset B)4);
and
C) a set of computer instructions stored in the Computer Software Storage Medium for calculating the difference by subtracting the first delay time from the second delay time.

16 more elements

Dependencies are inferred from the claim text.