Implantable cardiac rhythm management device incorporating a programmable watchdog timer
AssigneeCardiac Pacemakers, Inc.
InventorsBrian P. Thomas, Doug M. Birkholz, Grant Corcoran
Life of this patent
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Abstract
A cardiac rhythm management device incorporates a programmable Watchdog timer that permits more stringent time constraints to be placed upon the execution of software/firmware strings during a design phase when a deterministic model is being created. Thus, when performing real-time system engineering analysis on the model, potential imperfections in the deterministic model can be captured and resolved, resulting in a more reliable CRMD that is less likely to electronically reset once implanted in a patient.
Claims5
A cardiac rhythm management device comprising means for sensing cardiac depolarization events;
- pulse generating means for delivering cardiac stimulating pulses to the heart;
- a microprocessor-based controller coupled to receive the electrical signals from the sensing means and connected in controlling relation to the pulse generating means, the microprocessor-based controller executing a program of instructions stored therein for producing control signals at timed intervals to the pulse generating means based, at least in part, on the electrical signals from the sensing means;
- and a Watchdog timer in the microprocessor-based controller for monitoring instruction execution time by the microprocessor-based controller and capable of producing a Watchdog Interrupt signal when more than a predetermined period of time is required for executing one or more instructions in said program, the length of the predetermined time period being a programmable parameter.
A method of debugging an implantable rhythm cardiac management device of the type incorporating a microprocessor-based controller and a pulse generator controlled by said microprocessor-based controller, the microprocessor configured to execute a program of instructions within predetermined time constraints, comprising the steps of:
- (a) providing a counter that is coupled to receive regularly occurring clock signals from the microprocessor-based controller;
- (b) including in the program of instructions counter reset instructions at predetermined points in a sequence of the instructions;
- (c) resetting the counter upon execution of the counter reset instructions;
- and
- (d) continuously comparing quantities contained in the counter with a first predetermined value for equality and generating an interrupt signal for reinitiating the microprocessor-based controller when the comparison obtains, said predetermined value being a programmable parameter.
Dependencies are inferred from the claim text.