Hardware implementation of a decimating finite impulse response filter
AssigneeLinear Technology Corporation
InventorFlorin A. Oprescu
Life of this patent
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Abstract
The invention provides apparatus and methods for generating the coefficients of a finite impulse response digital filter used in signal sample rate conversion. Sequence generation circuitry provides a discrete-time sequence x(n) that is coupled to a plurality of cascaded discrete-time integrators that generate the filter coefficients h(n). Bit serial and interleaved bit serial implementations are described that provide efficient coefficient generators. The described apparatus and methods also may be used to efficiently implement a finite impulse response digital filter for an oversampling analog-to-digital converter.
Claims30
An apparatus for generating a plurality of coefficients h(n) for a r-th order finite impulse response digital filter, the digital filter having a z-domain transfer function comprising the product of a first polynomial, a second polynomial and r-1 third polynomials, the first polynomial comprising the z-transform of a predetermined discrete-time sequence g(n), the second polynomial and the r-1 third polynomials each comprising a z-domain transfer function of a discrete-time integrator, the apparatus comprising:
- input circuitry for generating a discrete-time sequence x(n), the sequence x(n) comprising the discrete-time integral of the sequence g(n);
- and
- a cascade of r-1 discrete-time integrators, the cascade comprising an input and an output, the input coupled to receive the sequence x(n), and the output providing the plurality of coefficients h(n).
An apparatus for generating a plurality of coefficients h(n) for an r-th order finite impulse response digital filter, the digital filter having a z-domain transfer function comprising the product of a first polynomial, a second polynomial and r-1 third polynomials, the first polynomial comprising the z-transform of a predetermined discrete-time sequence g(n), the second polynomial and the r-1 third polynomials each comprising a z-domain transfer function of a discrete-time integrator, the apparatus comprising:
- input circuitry for generating first and second portions of a discrete-time sequence x(n), the sequence x(n) comprising the discrete-time integral of the sequence g(n);
- and
- a cascade of interleaved serial arithmetic blocks, the cascade comprising first and second inputs and first and second outputs, the first input coupled to receive the first portion of sequence x(n), the second input coupled to receive the second portion of sequence x(n), the first output providing a first portion of the plurality of coefficients h(n), the second output providing a second portion of the plurality of coefficients h(n).
An apparatus for generating the coefficients of a finite impulse response digital filter.
A finite impulse response digital filter for filtering a discrete-time input sequence SIGIN to provide a discrete-time output sequence SIGOUT, the filter comprising:
- a sequence generator circuit that provides at a first output a first portion of a predetermined discrete-time coefficient sequence x(n) and that provides at a second output a second portion of the coefficient sequence x(n);
- a cascade of interleaved serial arithmetic blocks, the cascade comprising a first input coupled to the first output of the sequence generator and a second input coupled to the second output of the sequence generator, the cascade providing at a first output a first portion of a plurality of coefficients h(n) of the digital filter, and providing at a second output a second portion of the coefficients h(n);
- first and second combinatorial logic circuits each comprising first and second inputs and an output, the first input of the first combinatorial logic circuit coupled to the first output of the cascade, the second input of the first combinatorial logic circuit coupled to receive a first portion of the input sequence SIGIN, the first input of the second combinatorial logic circuit coupled to the second output of the cascade, the second input of the second combinatorial logic circuit coupled to receive a second portion of the input sequence SIGIN;
- a convolution circuit comprising a first input coupled to the output of the first combinatorial logic circuit, and a second input coupled to the output of the second combinatorial logic circuit, the convolution circuit providing at a first output a first portion of the output sequence SIGOUT, and providing at a second output a second portion of the output sequence SIGOUT.
A method for generating a plurality of coefficients h(n) for an r-th order finite impulse response digital filter, the digital filter having a z-domain transfer function comprising the product of a first polynomial, a second polynomial and r-1 third polynomials, the first polynomial comprising the z-transform of a predetermined discrete-time sequence g(n), the second polynomial and the r-1 third polynomials each comprising a z-domain transfer function of a discrete-time integrator, the method comprising:
- providing first and second portions of a discrete-time sequence x(n), the sequence x(n) comprising the discrete-time integral of the sequence g(n);
- and
- providing the first and second portions of the sequence x(n) to first and second inputs of a cascade of interleaved serial arithmetic blocks, the cascade comprising a first output providing a first portion of the plurality of coefficients h(n), and comprising a second output providing a second portion of the plurality of coefficients h(n).
Dependencies are inferred from the claim text.