Transceiver circuit transmitting/receiving a tenary pulse signal

A transceiver circuit for transmitting or receiving a ternary pulse signal carrying information data through two balanced transmission lines, comprising:

• a coupling transformer having a primary winding with one end and the other end thereof connected to said balanced transmission lines;
• a first tristate buffer having an output terminal thereof connected to one end of a secondary winding of said coupling transformer;
• a second tristate buffer having an output terminal thereof connected to the other end of said secondary winding of said coupling transformer;
• and
• a transmission/reception driving control circuit responsive to said information data to be transmitted for intermittently generating a first driving pulse signal having a predetermined high potential to supply said first driving pulse signal to an input terminal of said first tristate buffer, while intermittently generating a second driving pulse signal having said high potential at a timing different from said first driving pulse signal to supply said second driving pulse signal to an input terminal of said second tristate buffer, and further for controlling said first tristate buffer and said second tristate buffer such that said first tristate buffer and said second tristate buffer are enabled only at a timing at which said first driving pulse signal or said second driving pulse signal is generated.