Highly scalable architecture for implementing switch fabrics with quality of services
AssigneeCypress Semiconductor Corporation
InventorS. Babar Raza
Life of this patent
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Abstract
An apparatus comprising a plurality of interface circuits, a plurality of transmit outputs and a plurality of receive inputs. The plurality of interface circuits each comprises (i) a transmit circuit and (ii) a receive circuit. One of the plurality of transmit outputs is generally connected to one of the plurality of receive circuits. One of the plurality of receive inputs is generally connected to one of the plurality of transmit circuits. In general, each one of the plurality of the transmits outputs are generally connected to one of the plurality of the receive inputs.
Claims20
An apparatus comprising:
- a plurality of interface circuits each comprising (i) a transmit circuit comprising a plurality of transmit outputs, (ii) a receive circuit comprising a plurality of receive inputs and (iii) a scheduler circuit configured to control said transmit and receive circuits, wherein each one of said plurality of transmit outputs of one of said plurality of interface circuits is connected to one of said plurality of receive inputs of another of said plurality of interface circuits.
An apparatus comprising:
- a plurality of interface means each comprising (i) transmit means comprising a plurality of transmit outputs, (ii) receive means comprising a plurality of receive inputs and (iii) scheduler means configured to control said transmit means and said receive means, wherein each one of said plurality of transmit outputs of one of said plurality of interface means is connected to one of said plurality of receive inputs of another of said plurality of interface means.
A method for providing a switch fabric, comprising the steps of:
- (A) providing a plurality of interface circuits each comprising (i) a transmit circuit having a plurality of transmit outputs, (ii) a receive circuit having a plurality of receive inputs and (iii) a scheduler circuit configured to control said transmit and receive circuits;
- and
- (B) connecting each one of said plurality of transmit outputs of one of said plurality of interface circuits to one of said plurality of receive inputs of another of said plurality of interface circuits.
Dependencies are inferred from the claim text.