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US 6,603,706 B1Granted
Method and apparatus for synchronization of read data in a read data synchronization circuit
AssigneeLSI Logic Corporation
InventorsJohn M. Nystuen, Gregory F. Hammitt
Life of this patent
Estimating the term…
Abstract
A read data synchronization circuit for use in a Double Data Rate (DDR) memory system is provided. The read data synchronization circuit provides programmable timing signals for use in synchronizing read data.
Claims20
A read data synchronization circuit for use in a Double Data Rate (DDR) memory system, comprising:
- a read data line configured to couple to a bi-directional data bus (DQ);
- a data strobe line configured to couple to a bi-directional data strobe bus (DQS);
- a first data even transition circuit having an input coupled to the read data line which is clocked by a strobe pulse on the data line and a read data even output which is clocked by a clock signal;
- a first data odd transition circuit having an input coupled to the read data line which is clocked by a strobe pulse on the data line and a read data odd output which is clocked by a clock signal;
- and
- a command generation circuit configured to provide programmable enable signals to the enable inputs of the data even output which is enabled in response to an enable input transition circuit and the data odd output which is enabled in response to an enable input transition circuit.
3 more elements
A method for reading data in a double data rate (DDR) memory system, comprising:
- receiving read data on a bi-directional data bus (DQ);
- receiving a data strobe on a bi-directional data strobe bus (DQS);
- clocking read data into a read data even transition circuit based upon a strobe pulse from the data strobe bus;
- clocking read data into a read data odd transition circuit based upon a strobe pulse from the data strobe bus;
- enabling the read data even transition circuit to provide a read data even output;
- enabling the read odd transition circuit to provide a read data odd output;
- and
- generating programmable enable signals applied to enable inputs of the data even and second data odd transition circuits.
5 more elements
A read data synchronization circuit for use in a double data rate (DDR) memory system, comprising:
- means for receiving read data on a bi-directional data bus (DQ);
- means for receiving a data strobe on a bi-directional data strobe bus (DQS);
- means for read data into a first read data even register based upon a strobe pulse from the data strobe bus;
- means for read data into a first read data odd register based upon a strobe pulse from the data strobe bus;
- means for enabling a second data even register coupled to the first data read register configured to provide a read data even output;
- means for a second data odd register coupled to the first data read register configured to provide a read data odd output;
- and
- means for generating programmable enable signals applied to enable inputs of the second data even and second data odd registers.
5 more elements
Dependencies are inferred from the claim text.