Method of allowing random access to rambus DRAM for short burst of data
AssigneePMC-Sierra, Inc.
InventorsJason Chen, Henry Chow, Mark William Janoska
Life of this patent
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AssigneePMC-Sierra, Inc.
InventorsJason Chen, Henry Chow, Mark William Janoska
Estimating the term…
Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size. Within each frame, the read addresses to be accessed by read memory operations can be rearranged to minimize memory bank access conflicts with either write addresses to be accessed by write memory operations or other read addresses.
A method of increasing the efficiency of memory access operations to a memory subsystem having multiple memory banks, the method comprising arranging memory access operations to the memory banks such that the memory access operations follow a predetermined repeating pattern, the repeating pattern comprising a write memory access operation followed by a read memory access operation, each repetition of the repeating pattern being followed by a set time gap during which no memory access operation may be undertaken, the set time gap being a fixed, predetermined amount of time.
A method of selecting a write address for a write memory access operation to avoid possible memory bank contention between successive memory access operation, the method comprising selecting a write address based on the following criteria:
A method of increasing an efficiency of read memory access operations by avoiding possible memory bank contention between read memory access operations, the method comprising:
Dependencies are inferred from the claim text.