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US 6,603,704 B2Granted
Reduced current address selection circuit and method
AssigneeMicron Technology, Inc.
InventorAlan J. Wilson
Life of this patent
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AssigneeMicron Technology, Inc.
InventorAlan J. Wilson
Estimating the term…
An address selection circuit and method selects an internal address from a plurality of input address signals and avoids unnecessary signal transitions to reduce current consumption. A latch coupled to the outputs of first and second transfer gates latches either the first or second of the respective input address signals as the internal address and maintains the logic level of the input address signal even after enable signals for each of the transfer gates becomes inactive to prevent unnecessary transitions in the internal address.
An address selection circuit coupled to an address latch and decoder circuit, comprising:
An address selection circuit for selecting an internal address from a plurality of input address signals and providing the internal address to an address latch and decoder circuit, comprising:
An address selection circuit for selecting an internal address signal from a plurality of input address signals and providing the internal address signal to an address latch and decoder circuit, the address selection circuit coupling an input address signal based on an address internally generated by the memory device to a node in response to an active refresh command, coupling an input address signal based on an externally generated address to the node in response to an active enable signal, latching as the internal address signal a logic level of the input address signal of either the internally generated address or the externally generated address when the respective input address signal is coupled to the node, and maintaining the logic level of the internal address signal at the node after the address latch and decoder circuit has latched internal address signal and the refresh command or enable signal becomes inactive.
A memory device, comprising:
A computer system, comprising:
A method for selecting from a plurality of input address signals an internal address signal, the method comprising:
A method for selecting an internal address signal in a memory device, comprising:
A method for selecting an internal address signal in a memory device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders
Arrangements for selecting an address in a digital store: address interface arrangements, e.g. address buffers
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
Static stores
Term ended 26 Sep 2021 (estimated)
The present invention relates to memory devices, and more particularly to address selection circuitry having lower current consumption during an internal address selection operation.
Dynamic Random Access Memories (“DRAMs”) are commonly used in a variety of electronic devices, such as computers. A high level block diagram of a typical DRAM is shown in FIG. 1. The DRAM shown in FIG. 1 is a synchronous dynamic random access memory (“SDRAM”) 100, although the principles described herein are applicable to any memory device having a need for internal address selection circuitry. The SDRAM 100 includes an address register 104 that receives row addresses and column addresses on a multiplexed address bus. The address bus is generally coupled to a memory controller (not shown) which provides the row and column addresses.
Typically, a row address is initially received by the address register 104 and applied to a row address multiplexer 108. The row address multiplexer 108 couples the row address to a number of components associated with memory banks 130a-d, depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 130a-d is a respective row address latch/decoder 120a-d which stores the row address and applies various signals to its respective array 130a-d as a function of the stored row address. The row address multiplexer 108 also couples row addresses to the row address latches 120a-d for the purpose of refreshing the memory cells in the arrays 130a-d. The row addresses are generated for refresh purposes by a refresh counter 110. As will be described in greater detail below, the row address multiplexer 108 includes address selection circuitry 109 that selects between providing the external address received from the address register 104 and the address received from the refresh counter 110 to the row address latch/decoder 120a-d as an internal address.
FIG. 1 is a block diagram of a conventional memory device.
FIG. 2 is a schematic drawing of an address selection circuit.
FIG. 3 is a timing diagram of various signals related to the address selection circuit of FIG. 2.
Embodiments of the present invention are directed to a method and apparatus for selecting an internal address having reduced current consumption. Certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention.
FIG. 4 illustrates an address selection circuit 400 according to an embodiment of the present invention. The address selection circuit 400 includes a transfer gate 402 having an input to which one bit of the external address is applied and an output coupled to a latch circuit 420. The transfer gate 402 couples the external address applied to the latch circuit 420 in response to a HIGH ARA signal. A transfer gate 404 is also included in the address selection circuit 400. The transfer gate 404 has an input to which one bit of the CBR address is applied and an output coupled to the latch circuit 420. The output of a two-input NOR gate is coupled to the control terminals of the transfer gate 404. Thus, the transfer gate 404 couples the CBR address applied to its input to the latch circuit 420 in response to either an auto-refresh command signal AREF_H or a self-refresh command signal SREF_EN having a HIGH logic level.
The operation of the address selection circuit 400 will be explained with respect to the timing diagram illustrated in FIG. 5. As previously discussed with respect to the timing diagram of FIG. 3, the ARA signal is strobed twice during a memory access operation. As illustrated in FIG. 5, the ARA signal is active a first time between times T0 and T1 to latch a row address corresponding to the row of memory that will be activated during the memory access operation. The ARA signal is active a second time between times T2 and T3 to latch the row address of the row of memory to be deactivated to complete the memory array access operation.