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US 6,603,703 B2Granted
Dynamic memory word line driver scheme
AssigneeMosaid Technologies Incorporated
InventorValerie L. Lines
Life of this patent
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AssigneeMosaid Technologies Incorporated
InventorValerie L. Lines
Estimating the term…
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines for application to the enable inputs whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.
A method of selecting a word line in a dynamic random access memory to store a Vdd logic level in a memory cell comprising:
A method of selecting a word line in a dynamic random access memory to store a logic level in a memory cell comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
Static stores
Term ended 5 Apr 2011 (estimated)
This invention relates to CMOS dynamic random access memories (DRAMs), and particularly to word line drivers.
Dynamic random access memories are generally formed of a matrix of bit lines and word lines with memory cells located adjacent the intersections of the bit lines and word lines. The memory cells are enabled to provide their stored bits to the bit lines or to permit a write operation by signals carried on the word lines.
Each memory cell is typically formed of a bit storage capacitor connected to a reference voltage and through the source-drain circuit of an “access” field effect transistor to an associated bit line. The gate of the field effect transistor is connected to the word line. A logic signal carried by the word line enables the transistor, thus allowing charge to flow through the source-drain circuit of the transistor to the capacitor, or allowing charge stored on the capacitor to pass through the source-drain circuit of the access transistor to the bit line.
A better understanding of the invention will be obtained by reference to the detailed description below, in conjunction with the following drawings, in which:
FIG. 1 is a schematic diagram of the invention.
Turning now to FIG. 1, a CMOS DRAM is comprised of word lines, represented by word line 1 and bit lines, represented by bit lines 2A, 2B, etc. Access transistors 3A, 3B have their gates connected to the word line; their sources are connected to bit charge storing capacitors 4A, 4B, etc. which are also connected to ground. The drains of access transistors 3A, 3B, etc. are connected to the bit lines 2A, 2B, etc.
With the application of a logic signal of Vdd+Vtn to the gate of transistor 3A, 3B, etc., Vdd level on the bit line 2A, 2B, etc. is fully transferred to the associated capacitor 4A, 4B, etc. during the writing cycle. In the prior art it was necessary to apply a voltage greater than Vdd+2Vtn to the gate of an N-channel pass transistor in order to ensure that a voltage in excess of Vdd+Vtn would be available at the gates of transistors 3A, 3B, etc.
The combination of a bit storing charge capacitor, e.g. 4A, with an associated access transistor, e.g. 3A, forms a memory cell in prior art DRAMs.