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US 6,603,702 B2Granted
Semiconductor integrated circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMakoto Kojima
Life of this patent
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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMakoto Kojima
Estimating the term…
In a flash memory, a level shifter and a driver of a wordline driver are formed by MOS transistors having a low sustaining voltage, and a voltage control circuit for controlling a driver power supply voltage VPP is provided. The voltage control circuit holds VPP at a voltage LV which is below the sustaining voltage, when the logical state of the MOS transistors is changed. In addition, the voltage control circuit ramps up VPP from the low-level voltage LV to a voltage HV which is above the sustaining voltage, after the logical state of the MOS transistors has been changed. Further, the voltage control circuit ramps down VPP from the high-level voltage HV to the low-level voltage LV, before the logical state of the MOS transistors is changed next. Such arrangement enables even a wordline driver of the low-level voltage specification to handle not only low-level voltage but also high-level voltage without introducing any problems.
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
Programming or data input circuits: programming voltage switching circuits
Static stores
Term ended 11 Mar 2021 (estimated)
This invention relates to a semiconductor integrated circuit including a transistor designed to selectively provide either a low or a high voltage.
There has been the constraint imposed on the use condition of conventional MOS (metal-oxide semiconductor) transistors that the drain-source voltage Vds should not exceed a sustaining voltage Vds(sus), the reason for which is as follows. If Vds exceeds Vds(sus) when a drain-source current Ids is flowing, then avalanche breakdown occurs, resulting in a rapid increase in Id (the drain current). Vds(sus) is the voltage below the drain-source breakdown voltage BVds which is defined on the condition that the gate-source voltage Vgs is equal to 0 V. The breakdown voltage defined by Vds(sus) is called the “sustaining breakdown voltage”. Further, the same sustaining breakdown voltage constraint is imposed also on bipolar transistors.
FIG. 1 shows characteristics of an N channel MOS transistor by measurements at room temperature. The gate oxide film thickness, the gate length, and the BVds of the transistor are, 8 nm, 0.4 μm, and about 7 V, respectively. As can be seen from FIG. 1, the Vds(sus) of the transistor is 4.0 V. FIG. 1 shows that if Vds increases beyond Vds(sus) when Vgs is held at, for example, 3.0 V, avalanche breakdown occurs and there is a sudden increase in Id. This phenomenon may be explained as follows. Electrons, i.e., carriers forming Ids, are accelerated by a high electric field at the drain end. The accelerated electrons generate an electron-hole pair by collision. The generated electron, accelerated with high energy, jumps into the gate oxide film. On the other hand, the generated hole is observed as a substrate current Isub superimposing Ids and there is appeared a sudden increase in Id (=Ids+Isub). Such a phenomenon is called the “hot carrier effect” which is a known cause of transistor reliability problems. Accordingly, the power supply voltage, when the transistor of FIG. 1 is used, is limited to voltage values below Vds(sus), for example, 3.3 V. Also for the case of P channel MOS transistors, the hot carrier effect more or less exists, and the same as pointed out above for the N channel MOS transistor can be applied for the P channel MOS transistor.
FIG. 1 is a transistor characteristic diagram for the purpose of providing a description of the sustaining voltage of an N channel MOS transistor.
FIG. 2 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to the present invention.
FIG. 3 is a circuit diagram showing in detail an example of the configuration of a wordline driver in FIG. 2.
Referring to FIG. 2, there is shown an exemplary configuration of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit of FIG. 2 is a flash memory which includes a memory cell array 10, a row decoder 20, a wordline driver 30, and a voltage control circuit 40. The memory cell array 10 is made up of a large number of nonvolatile memory cells 15 of the floating gate type, each nonvolatile memory cell 15 having a control gate. In FIG. 2, WL0, WL1, . . . , WLn are wordlines. SL0, SL1, . . . , SLn are source lines. BL is a bitline. WL0, WL1, . . . , WLn are connected to the control gates of their corresponding nonvolatile memory cells 15. The wordline driver 30 comprises a level shifter 31 for converting an address decode signal into a signal at the level of a driver power supply voltage VPP controlled by the voltage control circuit 40 and a driver 32 for driving, in response to an output signal from the level shifter 31, a corresponding one of the wordlines WL0, WL1, . . . , WLn with the VPP-level logical signal. The row decoder 20 is a decoder for generating from an address (ADRS) signal an address decode signal to be supplied to each level shifter 31 for selection of a row in the memory cell array 10. The voltage control circuit 40 is a circuit for connecting, in response to a selection (SEL) signal, either one of a high voltage (HV) power supply and a low voltage (LV) power supply to a VPP feed line. Note that the power supply of the row decoder 20 is fixed at LV.
More concretely, the nonvolatile memory cell 15 is a cell of the channel hot electron (CHE) type and the writing of an information bit to the nonvolatile memory cell 15 is performed by application of 6 V to the control gate (see S. Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, IEDM 1998, pp. 987-990). Accordingly, for example, LV=3.3 V and HV=6 V. Further, the flash memory of FIG. 2 is used for storage of instruction codes and is mounted on the same semiconductor chip that the microcontroller is mounted. This type of memory is called “the code ROM” which is factory-programmed only once and can only be read thereafter. The cycle time of programming and erase ranges from several tens of microseconds to several hundreds of milliseconds, and the cycle time of read is about several tens of nanoseconds.
FIG. 3 shows an exemplary detailed configuration of the wordline driver 30 in FIG. 2. The row decoder 20 has a latch LT for holding an address decode (DEC) signal and two inverters INV1 and INV2. The inverters INV1 and INV2 provide their respective outputs to the level shifter 31. The level shifter 31 is made up of two P channel MOS transistors P1 and P2 connected to VPP to form a latch and two N channel MOS transistors N1 and N2 placed on the ground side. The outputs of INV1 and INV2 are fed to the gate of N2 and to the gate of N1, respectively. The driver 32 is formed by a CMOS inverter 2-stage configuration made up of two P channel MOS transistors P3 and P4 connected to VPP and two N channel MOS transistors N3 and N4 placed on the ground side. The level shifter 31 and the driver 32 for each wordline WL0, WL1, . . . , WLn are each configured as shown in FIG. 3.