Memory device and computer system including circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
AssigneeMicron Technology, Inc.
InventorLeel S. Janzen
Life of this patent
Estimating the term…
Abstract
A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The circuit includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.
Claims14
A memory device, comprising:
- an address decoder coupled to an address bus;
- a read/write circuit coupled to a data bus;
- a control circuit coupled to a control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array storing dynamic data;
- and
- a refresh controller coupled to the memory-cell array, control circuit and address decoder for controlling a refresh rate of the dynamic data, the refresh controller being adapted to receive a supply voltage and including a refresh oscillator that generates a refresh clock signal having a frequency that is a function of a bias voltage, the refresh controller operable in a normal mode when the magnitude of the supply voltage is greater than a minimum value to apply a substantially constant bias voltage to the refresh oscillator and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a first refresh rate having a value determined by the frequency of the refresh clock signal, and the refresh controller operable in a low-power mode when the magnitude of the supply voltage is less than or equal to the minimum value to vary the bias voltage as a function of the magnitude of the supply voltage and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a second refresh rate having a variable value that is a function of the frequency of the refresh clock signal.
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device including,
- an address decoder coupled to an address bus;
- a read/write circuit coupled to a data bus;
- a control circuit coupled to a control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array storing dynamic data;
- and
- a refresh controller coupled to the memory-cell array, control circuit, and address decoder for controlling a refresh rate of the dynamic data, the refresh controller being adapted to receive a supply voltage and including a refresh oscillator that generates a refresh clock signal having a frequency that is a function of a bias voltage, the refresh controller operable in a normal mode when the magnitude of the supply voltage is greater than a minimum value to apply a substantially constant bias voltage to the refresh oscillator and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a first refresh rate having a value determined by the frequency of the refresh clock signal, and the refresh controller operable in a low-power mode when the magnitude of the supply voltage is less than or equal to the minimum value to vary the bias voltage as a function of the magnitude of the supply voltage and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a second refresh rate having a variable value that is a function of the frequency of the refresh clock signal.
Dependencies are inferred from the claim text.