Semiconductor memory device having self-refresh mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKatsuyoshi Mitsui
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Abstract
An address generating circuit of a DRAM includes five fuses, a trimming switching circuit generating five signals in accordance with whether or not each fuse is blown, a voltage converting circuit generating a control voltage of a level corresponding to the five signals, a voltage control oscillation circuit generating a clock signal of a cycle according to the control voltage, and an address counter generating an address signal in synchronization with the clock signal. Thus, unlike a conventional example, a plurality of counting circuits and a detection circuit are eliminated, resulting in reduction of power consumption and circuit scale.
Claims6
A semiconductor memory device, provided with a plurality of memory cell rows and having a self-refresh mode, comprising:
- a voltage control oscillation circuit generating a clock signal with a cycle according to a control voltage;
- a refresh execution circuit activated during said self-refresh mode, to sequentially select said plurality of memory cell rows in synchronization with said clock signal and to refresh data in selected memory cell rows;
- a signal generating circuit including at least one fuse, and outputting a signal for setting a cycle of said clock signal based on whether or not the fuse is blown;
- and
- a voltage generating circuit generating said control voltage for said voltage control oscillation circuit in accordance with an output signal of said signal generating circuit.
Dependencies are inferred from the claim text.