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US 6,603,693 B2Granted
DRAM with bias sensing
AssigneeMicron Technology, Inc.
InventorsScott Derner, Casey Kurth, Phillip G. Wald
Life of this patent
Estimating the term…
Abstract
A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an un-programmed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.
Claims20
A DRAM memory device comprising:
- a plurality of memory cell capacitors;
- row lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry couplable to first and second digit lines;
- a reference line containing a charge having a voltage of X, where Vss<X<½ Vcc, the reference line is couplable to the second digit line;
- and
- control circuitry to activate one of the row lines and couple the second digit line to the sense amplifier such that the second digit line voltage is reduced below ½ Vcc.
3 more elements
A DRAM memory device comprising:
- a plurality of memory cell capacitors;
- row lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry couplable to first and second digit lines;
- a reference line coupled to a reference voltage X, where Vss<X<½ Vcc, the reference line is couplable to the second digit line;
- and
- control circuitry to activate one of the row lines and couple the second digit line to the sense amplifier such that the second digit line voltage is reduced below ½ Vcc.
3 more elements
A DRAM memory device comprising:
- a plurality of memory cell capacitors;
- row lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry coupled to first and second digit lines;
- a reference line coupled to a reference voltage X, where ½ Vcc<X<Vcc, the reference line is couplable to a reference digit line;
- and
- control circuitry to activate one of the row lines and couple the reference digit line to the sense amplifier such that the reference digit line voltage is reduced below ½ Vcc.
3 more elements
A DRAM memory device comprising:
- a plurality of memory cell capacitors;
- row lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry couplable to first and second digit lines;
- a reference row couplable to a non-volatile reference cell, the reference cell is programmed to conduct a specific current in response activating the reference row;
- and
- control circuitry to activate one of the row lines and couple the reference row line to the second digit line for a predetermined time.
3 more elements
A method of reading a memory cell comprising:
- equilibrating first and second digit lines to a common voltage;
- accessing the memory cell and coupling the memory cell to the first digit line;
- coupling a reference cell to the second digit line, wherein the reference cell decreases a voltage of the second digit line below the common voltage;
- and
- sensing a differential voltage between the first and second digit lines.
2 more elements
A method of reading a DRAM memory cell comprising:
- equilibrating first and second digit lines to a common voltage;
- accessing the DRAM memory cell and coupling the memory cell to the first digit line;
- coupling a discharged DRAM reference memory cell to the second digit line, wherein the discharged DRAM reference memory cell decreases a voltage of the second digit line below the common voltage;
- and
- sensing a differential voltage between the first and second digit lines.
2 more elements
A method of reading a DRAM memory cell comprising:
- equilibrating first and second digit lines to a voltage of ½ Vcc;
- accessing the DRAM memory cell and coupling the memory cell to the first digit line;
- coupling a ROM memory cell to the second digit line, wherein the ROM memory cell is coupled to a reference voltage X, where ½ Vcc<X<Vcc, such that the ROM memory cell decreases a voltage of the second digit line below ½ Vcc;
- and
- sensing a differential voltage between the first and second digit lines.
2 more elements
A method of reading a DRAM memory cell comprising:
- equilibrating first and second digit lines to a voltage of ½ Vcc;
- accessing the DRAM memory cell and coupling the memory cell to the first digit line;
- coupling the second digit line to a voltage supply having a voltage X, where ½ Vcc<X<Vcc, wherein the second digit line is coupled to the voltage supply for a pre-determined time such that a voltage of the second digit is decreased below ½ Vcc;
- and
- sensing a differential voltage between the first and second digit lines.
2 more elements
A method of reading a DRAM memory cell comprising:
- equilibrating first and second digit lines to a voltage of ½ Vcc;
- accessing the DRAM memory cell and coupling the memory cell to the first digit line;
- coupling a ROM memory cell to the second digit line, wherein the ROM memory cell is coupled to a reference voltage X, where Vss<X<½ Vcc, such that the ROM memory cell decreases a voltage of the second digit line below ½ Vcc;
- and
- sensing a differential voltage between the first and second digit lines.
2 more elements
Dependencies are inferred from the claim text.