Semiconductor device including built-in redundancy analysis circuit for simultaneously testing and analyzing failure of a plurality of memories and method for analyzing the failure of the plurality of memories

Abstract

A semiconductor device including a built-in redundancy analysis (BIRA) circuit for simultaneously testing and analyzing failures of a plurality of memories, and a failure analyzing method, includes a plurality of memory blocks, a plurality of built-in redundancy analysis units for outputting a group of failure repairing information signals by testing and analyzing a corresponding memory block among the plurality of memory blocks in response to common driving signals and each of independent selection signals, and a controller for generating the common driving signals and the respective independent selection signals in response to a plurality of externally applied control signals and sequentially receiving and sequentially outputting the group of failure repairing information signals generated from the respective built-in redundancy analysis units. According to the semiconductor device and the failure analyzing method, it is possible to reduce the test time and expense since a plurality of memories having different sizes can be simultaneously tested and analyzed.

Dependencies are inferred from the claim text.