Semiconductor memory device having redundancy system
AssigneeKabushiki Kaisha Toshiba
InventorsDaisuke Kato, Yohji Watanabe
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Abstract
A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.
Claims34
A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising:
- a plurality of fuse sets each including address fuses for programming a defective address in the memory system;
- and
- a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used,
- wherein at least one master fuse is shared by at least two fuse sets among the plurality of fuse sets.
A redundancy system for a semiconductor memory device, comprising:
- a fuse bank having a plurality of juxtaposed fuses;
- fuse latch circuits corresponding to the plurality of fuses, respectively;
- a plurality of address signal wirings corresponding to the plurality of address fuses in the fuse bank;
- and
- a plurality of address comparators to which address signals are supplied via the address signal wirings;
- wherein at least one of the address signal wirings and the address comparators is disposed in a side opposite to a side where the fuse latch circuits are disposed with respect to the fuse bank.
A redundancy system of a semiconductor memory device, comprising:
- a first fuse bank having a plurality of juxtaposed fuses;
- a second fuse bank disposed in parallel with the first fuse bank and having a plurality of juxtaposed fuses;
- a plurality of address signal wirings corresponding to the plurality of address fuses in the first and second fuse banks;
- and
- a plurality of address comparators to which address signals are supplied via the address signal wirings;
- wherein at least one of the address signal wirings and the address comparators is disposed in the outside of the row of the first and second juxtaposed fuse banks.
A redundancy system of a semiconductor device with a memory system, comprising:
- a plurality of redundant elements for relieving a defect in the memory system;
- a plurality of fuse sets including a plurality of address fuses for programming a defective address in the memory system and corresponding to the redundant elements;
- a plurality of control circuits to which a signal having information whether or not a state of an address fuse of one bit in the fuse set agrees with a corresponding address signal is supplied;
- a fuse bank in which the plurality of fuse sets are disposed;
- and
- a plurality of fuse latch circuits corresponding to the plurality of fuses, respectively;
- wherein at least one of the control circuits is disposed in a side opposite to the side where the fuse latch circuits are disposed with respect to the fuse bank.
A redundancy system of a semiconductor device with a memory system, comprising:
- a plurality of redundant elements for relieving a defect in the memory system;
- a plurality of fuse sets including a plurality of address fuses for programming a defective address in the memory system and corresponding to the redundant elements;
- a plurality of control circuits to which a signal having information whether or not a state of an address fuse of one bit in the fuse set agrees with a corresponding address signal is supplied;
- a first fuse bank in which the plurality of fuse sets are disposed;
- and
- a second fuse bank disposed in parallel with the first fuse bank and having a plurality of fuse sets;
- wherein at least one of the control circuits is disposed in the outside of the row of the first and second fuse banks.
Dependencies are inferred from the claim text.