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US 6,603,688 B2Granted
Semiconductor memory device having improved arrangement for replacing failed bit lines
AssigneeHitachi, Ltd.
InventorsMasatoshi Hasegawa, Kazuhiko Kajigaya
Life of this patent
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Abstract
In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.
Claims20
A semiconductor memory device, comprising:
- a plurality of memory mats arranged in a direction of bit-line which including bit lines, word lines and memory cells coupled to said bit lines and said word lines;
- a MOSFET included in each of said memory cells and having a capacitance having first and second electrodes, a gate coupled to a corresponding one of said word lines and source-and-drain paths one of which is coupled to a corresponding one of said bit lines and the other is coupled to said first electrode of said capacitance;
- and
- a amplifier circuit provided in a region between said memory mats arranged in a direction of said bit line and having unit-amplifier circuits connected to bit line pairs separately provided to two of said memory mats,
- wherein the number of said unit-amplifier circuits being less than the number of said bit line pairs;
- and
- wherein a failed bit line of said bit line pairs can be replaced, on a unit-amplifier basis, with a redundant bit line pair and a corresponding unit-amplifier circuit.
4 more elements
A semiconductor memory device, comprising:
- a plurality of memory array regions arranged in a first direction;
- a plurality of sense amplifier regions arranged alternate with said memory array regions;
- each of said memory array regions having a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second line orthogonal to the first line and a plurality of memory cells corresponding to said bit lines and said word lines;
- each of said sense amplifier region having therein a first sense amplifier connected to a first bit line in one region of said memory array regions on adjacent both sides of each sense amplifier region and a second bit line in the other region thereof and a second sense amplifier connected to a first redundant bit line in said one region and to a second redundant bit line in the other region;
- whereby, in the case that said first bit line in one memory array region is replaced with said first redundant bit line, said second bit line is to be replaced with said second redundant bit line.
2 more elements
A semiconductor memory device, comprising:
- a plurality of memory array regions arranged in a first direction;
- a plurality of sense amplifier regions arranged alternate with said memory array regions;
- each of said memory array regions having a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second line orthogonal to the first line and a plurality of memory cells corresponding to said bit lines and said word lines;
- each of said sense amplifier region having therein a first sense amplifier connected to a bit line in one region of said memory array regions on adjacent both sides of each sense amplifier region and a bit line in the other region thereof and a second sense amplifier connected to a redundant bit line in said one region and to a redundant bit line in the other region;
- whereby, in the case that a redundant bit line is selected in place of a predetermined bit line in one memory array region, said redundant bit line is selected in place of said predetermined bit line in another memory array region corresponding to said predetermined bit line in said one memory array region.
2 more elements
A semiconductor memory device, comprising:
- a plurality of memory array regions arranged in a first direction;
- a plurality of sense amplifier regions arranged alternate with said memory array regions;
- each of said memory array regions having a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second line orthogonal to the first line and a plurality of memory cells corresponding to intersections between said bit lines and said word lines;
- each of said sense amplifier region having therein a first sense amplifier connected to a first bit line in one region of said memory array regions on adjacent both sides of each sense amplifier region and a second bit line in the other region thereof and second sense amplifiers connected to first redundant bit lines in said one region and to second redundant bit lines in the other region;
- whereby, effected in one memory array region are bit relief to replace said first bit line with said first redundant bit line
- and bit relief, where in another memory array region said redundant bit line is selected in place of a predetermined bit line, to select said redundant bit line in place of said predetermined bit line in said memory array regions on both sides of said other memory array region.
3 more elements
A semiconductor memory device, comprising:
- a plurality of memory array regions arranged in a first direction;
- a plurality of sense amplifier regions arranged alternate with said memory array regions;
- each of said memory array regions having a plurality of bit line pairs extending in the first direction, a plurality of word lines extending in a second line orthogonal to the first line and a plurality of memory cells corresponding to ones of said bit line pairs and said word lines;
- each of said sense amplifier region having therein a first sense amplifier connected to a first bit line in one region of said memory array regions on adjacent both sides of each sense amplifier region and a second bit line in the other region thereof and a second sense amplifier connected to a first redundant bit line in said one region and to a second redundant bit line in the other region;
- whereby, effected in one memory array region can be bit relief on a bit-line basis to replace said first bit line that failure exists on said memory cell with corresponding one of said first redundant bit lines
- and bit relief on a bit-line-pair basis, when in one memory array region failure exists on said first bit line, both of said first and second bit lines can be replaced with said first and second redundant bit lines.
3 more elements
A Semiconductor memory device, including:
- a first bit line;
- a second bit line;
- a first redundant bit line;
- a second redundant bit line;
- a plurality of first memory cells connected to said first bit line;
- a plurality of second memory cells connected to said second bit line;
- a plurality of first redundant memory cells connected to said first redundant bit line;
- a plurality of second redundant memory cells connected to said second redundant bit line;
- a first amplifier circuit connected to said first bit line and said second bit line to amplify a difference of potential between said first bit line and said second bit line;
- and
- a first redundant amplifier circuit connected to said first redundant bit line and said second redundant bit line to amplify a difference of potential between said first redundant bit line and said second redundant bit line,
- wherein, in the case that said first bit line is failed and said second bit line is normal, said first bit line is replaced with said first redundant bit line and said second bit line is replaced with said second redundant bit line.
9 more elements
A Semiconductor memory device, including:
- a first bit line;
- a second bit line;
- a first redundant bit line;
- a second redundant bit line;
- a plurality of first memory cells connected to said first bit line;
- a plurality of second memory cells connected to said second bit line;
- a plurality of first redundant memory cells connected to said first redundant bit line;
- a plurality of second redundant memory cells connected to said second redundant bit line;
- a first amplifier circuit connected to said first bit line and said second bit line to amplify a difference of potential between said first bit line and said second bit line;
- and
- a first redundant amplifier circuit connected to said first redundant bit line and said second redundant bit line to amplify a difference of potential between said first redundant bit line and said second redundant bit line,
- wherein, selectable are a case that said first bit line is replaced with said first redundant bit line but said second bit line is not replaced with said second redundant bit line and a case that said first bit line is replaced with said first redundant bit line and said second bit line is replaced with said second redundant bit line.
9 more elements
Dependencies are inferred from the claim text.