Semiconductor devices, circuits and methods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop

A circuit in a semiconductor memory device that has a memory cell array, comprising:

• a delay control circuit to generate an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• at least one replica delay circuit defining a loop with the delay control circuit, the replica delay circuit to receive the internal clock signal at a beginning of the loop and to generate at an end of the loop the feedback clock signal from the received internal clock signal;
• a group of data input latches to input data into the memory cell array, and to synchronize inputting the data according to the internal clock signal received with a first delay from a first tapping point of the loop;
• and
• a group of data output buffers to buffer data received from the memory cell array, and to synchronize buffering the received data according to the internal clock signal received with a second delay from a second tapping point of the loop,
• and in which the replica delay circuit includes
• a fuse, and
• a compensation delay feature that has a delay which is adjustable by cutting the fuse.

A circuit in a semiconductor memory device that has a memory cell array, comprising:

• a delay control circuit to generate an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• a replica delay circuit to input the internal clock signal and to output the feedback clock signal;
• a group of data input latches to input data into the memory cell array, and to synchronize inputting the data according to the feedback clock signal;
• and
• a group of data output buffers to buffer data received from the memory cell array, and to synchronize buffering the received data according to the internal clock signal.

A circuit in a semiconductor memory device that has a memory cell array, comprising:

• a delay control circuit to generate an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• a first replica delay circuit to input the internal clock signal and to output an intermediate clock signal;
• a second replica delay circuit to input the intermediate clock signal and to output the feedback clock signal;
• a group of data input latches to input data into the memory cell array, and to synchronize inputting the data according to the intermediate clock signal;
• and
• a group of data output buffers to buffer data received from the memory cell array, and to synchronize buffering the received data according to the internal clock signal.

A circuit in a semiconductor device, comprising:

• a delay control circuit to generate an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• a first replica delay circuit to input the internal clock signal and to output an intermediate clock signal;
• a second replica delay circuit to input the intermediate clock signal and to output the feedback clock signal;
• a group of data input latches to input data into a semiconductor device, and to synchronize inputting the data according to the intermediate clock signal;
• and
• a group of data output buffers to output data from the semiconductor device, and to synchronize outputting the data according to the internal clock signal.

A semiconductor memory device comprising:

• means for generating an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• means for receiving the internal clock signal at a beginning of a loop and for generating at an end of the loop the feedback clock signal from the received internal clock signal;
• means for inputting data into a memory cell array;
• means for synchronizing inputting the data according to the internal clock signal received with a first delay from a first tapping point of the loop;
• means for outputting data received from the memory cell array;
• and
• means for synchronizing outputting the received data according to the internal clock signal received with a second delay from a second tapping point of the loop.

A semiconductor device comprising:

• means for generating an internal clock signal responsive to an input clock signal and to a feedback clock signal;
• means for receiving the internal clock signal at a beginning of a loop and for generating at an end of the loop the feedback clock signal from the received internal clock signal;
• means for inputting data into a semiconductor device;
• means for synchronizing inputting the data according to the internal clock signal received with a first delay from a first tapping point of the loop;
• means for outputting data from the semiconductor device;
• and
• means for synchronizing outputting the data according to the internal clock signal received with a second delay from a second tapping point of the loop.

A method for a semiconductor memory device having a memory cell array comprising:

• receiving an input clock signal having a first phase;
• delaying the received input clock signal by a first amount to generate an internal clock signal;
• delaying the internal clock signal along a single loop to generate a feedback clock signal having a second phase;
• controlling the first amount such that the second phase equals the first phase;
• receiving from a first tapping point of the loop a firstly delayed version of the internal clock signal;
• synchronizing, according to the firstly delayed version, a group of data input in the device for inputting in the memory cell array;
• receiving from a second tapping point of the loop a secondly delayed version of the internal clock signal;
• and
• synchronizing, according to the secondly delayed version, a group of data output from the memory cell array for outputting from the device.

A method for a semiconductor device comprising:

• receiving an input clock signal having a first phase;
• delaying the received input clock signal by a first amount to generate an internal clock signal;
• delaying the internal clock signal along a single loop to generate a feedback clock signal having a second phase;
• controlling the first amount such that the second phase equals the first phase;
• receiving from a first tapping point of the loop a firstly delayed version of the internal clock signal;
• synchronizing, according to the firstly delayed version, a group of data input in the device for inputting in a semiconductor device;
• receiving from a second tapping point of the loop a secondly delayed version of the internal clock signal;
• and
• synchronizing, according to the secondly delayed version, a group of data output from the memory cell array for outputting from the semiconductor device.