US 6,603,686 B2 · Semiconductor memory device having different data rates in read operation and write operation

Abstract

A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Claims6

Dependent claims

A method for controlling a data transfer from a semiconductor memory device to a memory controller, comprising:

a) generating a strobe signal synchronized to both a first read data signal and a second read data signal;
b) outputting the first read data signal at a rising edge of the strobe signal in a first read operation;
c) sampling the first read data signal in the memory controller;
d) outputting the second read data signal at a falling edge of the strobe signal in a second read operation;
and
e) sampling the second read data signal in the memory controller;
wherein the synchronized strobe signal and the first and second data signals are transferred together via a same length data path to the memory controller in the first and second read operations, respectively.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having different data rates in read operation and write operation

Life of this patent

Semiconductor memory device having different data rates in read operation and write operation

Life of this patent

Abstract

Claims6