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US 6,603,683 B2Granted
Decoding scheme for a stacked bank architecture
AssigneeInternational Business Machines Corporation
InventorsLouis Hsu, Li-Kong Wang
Life of this patent
Estimating the term…
Abstract
A decoding scheme for simultaneously executing multiple operations for a stacked-bank type semiconductor memory device is disclosed. A decoding unit is provided to a memory bank group comprising a plurality of memory banks. When read and write bank addresses match with two different memory banks within the same memory bank group, the decoding unit receives the read and write addresses and generates two different row selection signals for the read and write operations in two different banks. Based on the row selection signals, the row decoder unit in the two matching banks simultaneously activates a target row designated by the read/write addresses.
Claims25
A semiconductor memory device comprising:
- a plurality of memory bank groups, each memory bank group of said plurality of memory bank groups comprising a plurality of memory banks arranged in a stacked-bank architecture;
- an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks for read/write operations;
- a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks;
- wherein said address bus comprises a global address bus for transferring said read/write bank addresses and read/write addresses for said read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read/write bank addresses and read/write addresses to said decoding units, and
- wherein said read and write operations may be simultaneously performed in at least two respective memory banks of said each memory bank group.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;
- an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations;
- and
- a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks;
- wherein said address bus comprises a global address bus for transferring said read/write bank addresses and read/write addresses for said read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read/write bank addresses and read/write addresses to said decoding units, and
- whereby each memory bank group simultaneously executes at least two of said read, write and refresh operations at least two memory banks thereof.
3 more elements
An integrated circuit including a memory, said memory including:
- at least one memory bank group comprising a plurality of memory banks including at least a first memory bank and a second memory bank arranged in a stacked-bank architecture;
- an address bus coupled to said first memory bank and to said second memory bank to provide a write address and a read address to any combination of said first and said second memory banks, and to simultaneously transfer a write address to said first memory bank and a read address to said second memory bank, said read address being selected independently from said write address;
- and
- a plurality of decoding units provided corresponding to a plurality of said at least one memory bank group, each decoding unit transferring said read and write addresses to at least two memory banks of said plurality of memory banks if read and write bank addresses match said at least two memory banks;
- wherein said address bus comprises a global address bus for transferring said read and write bank addresses and said read and write addresses for read/write operations and a plurality of local address buses provided corresponding to said plurality of decoding units, each coupled between said global address bus and the corresponding decoding unit and transferring said read and write bank addresses and said read and write addresses to said decoding units;
- whereby, a write operation in said first memory bank may be performed simultaneously with an independent read operation in said second memory bank.
3 more elements
A semiconductor memory device comprising:
- a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;
- an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations;
- and
- a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit simultaneously transferring said read/write addresses to said at least two memory banks if said read/write bank addresses matches said at least two memory banks for said read/write/refresh operations, each of said plurality of decoding units comprising a plurality of register units provided corresponding to said plurality of memory banks of each memory bank group, each register unit generating a row selection signal for either said read operation or said refresh operation if said read bank address matches said corresponding bank and generating a row selection signal for said write operation if said write bank address matches said corresponding bank;
- wherein each memory bank group simultaneously executes at least one of (i) two of said read, write and refresh operations at least two memory banks thereof and (ii) either said read/write operations or said refresh/write operations at least two memory banks thereof.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory bank groups, each group comprising a plurality of memory banks arranged in a stacked-bank architecture;
- an address bus transferring read/write bank addresses and read/write addresses for locations in one or more memory banks of a memory bank group for read/write/refresh operations;
- and
- a plurality of decoding units provided corresponding to said plurality of memory bank groups, each decoding unit simultaneously transferring said read/write addresses to said at least two memory banks if said read/write bank addresses match said at least two memory banks for said read/write/refresh operations, each of said plurality of decoding units comprising a plurality of register units, each register unit comprising a plurality of multiplexing units, each multiplexing unit receiving said read address and generating a row selection bit signal for said read operation or said refresh operation if said read bank address matches said corresponding bank, and receiving said write address and generate a row selection bit signal for said write operation if said write bank address matches said corresponding bank;
- wherein each memory bank group simultaneously executes at least one of (i) two of said read, write and refresh operations at least two memory banks thereof and (ii) either said read/write operations or said refresh/write operations at least two memory banks thereof.
2 more elements
An integrated circuit including a memory, said memory including:
- at least one memory bank group comprising a plurality of memory banks including at least a first memory bank and a second memory bank arranged in a stacked-bank architecture, said memory bank group comprises a number n of memory banks;
- and
- an address bus coupled to said first memory bank and to said second memory bank to provide a write address and a read address to any combination of said first and said second memory banks, and to simultaneously transfer a write address to said first memory bank and a read address to said second memory bank, said read address being selected independently from said write address, said address bus includes a number m read paths and said number m write paths, 2m being less than or equal to n, such that said address bus is adapted to simultaneously transfer, one of m independently selected read addresses to each of m said memory banks and one of m independently selected write addresses to each of m other said memory banks, whereby m read operations and m write operations may be performed simultaneously in each of said 2m memory banks, and
- whereby a write operation in said first memory bank may be performed simultaneously with an independent read operation in said second memory bank.
1 more element
Dependencies are inferred from the claim text.