Non-volatile memory with block erase
AssigneeMicron Technology, Inc.
InventorBrady L. Keays
Life of this patent
Estimating the term…
Abstract
A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.
Claims10
A flash memory system comprising:
- a processor to provide external erase commands;
- a plurality of memory arrays, wherein each memory array has a plurality of erasable blocks of flash memory cells, further wherein the memory cells in each block are arranged in rows;
- a controller to receive the external erase commands from the processor, wherein the controller performs erase operations on the blocks of memory cells in the plurality of memory arrays;
- and
- a plurality of registers coupled to the controller to track rows of memory cells verified as being erased, each register is associated with one of the memory arrays, wherein each register has a plurality of register sub-blocks, each register sub-block is associated with a block of memory cells, further wherein each sub-block has a register memory cell for each row in its associated block of memory cells.
A method for erasing a non-volatile memory device in a flash memory system having a system processor, the method comprising:
- receiving an erase memory command from the system processor;
- a device controller generating, in response to the erase memory command, a first stage of erase pulses to a flash memory block to erase a predetermined quantity of rows of memory cells;
- the device controller counting the number of first stage erase pulses needed to erase the predetermined quantity of rows of memory cells;
- the device controller generating a second stage of erase pulses on the flash memory block to attempt erasure of rows of memory cells not erased by the first stage of erase pulses, the second stage of erase pulses being a fraction of the first stage of erase pulses;
- and
- the device controller updating a register array to indicate which rows of the flash memory block have been erased.
Dependencies are inferred from the claim text.