Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method

A pulse programming method for a non-volatile memory device, comprising the steps of:

• enabling a bias circuit including a drain voltage regulator having an output coupled to drain terminals of memory cells to be programmed in said memory device;
• addressing the memory cells to be programmed in said memory device by selecting corresponding hierarchic decoder transistors of said bias circuit;
• biasing gate terminals of said memory cells;
• precharging a parasitic capacitance connected to at least one of said hierarchic decoder transistors of said bias circuit;
• and
• programming said memory cells by applying a voltage pulse to the drain terminals of said memory cells.

A programming method for a non-volatile memory device, comprising the steps of:

• addressing row and columns to be programmed of a matrix of memory cells in said memory device by selecting a corresponding program load transistor and hierarchic transistors in a bias circuit;
• biasing gate terminals of said memory cells;
• precharging a parasitic capacitance, corresponding to a capacitive load of a column decoder, driving said hierarchic transistors;
• and
• completing a programming phase by applying a voltage pulse to drain terminals of said addressed memory cells.

A memory device, comprising:

• a non-volatile memory cell having a drain terminal;
• and
• a bias circuit for biasing the drain terminal of the memory cell, the bias circuit including:
• a column decoder portion, connected between a regulated voltage reference and said drain terminal, comprising a program load transistor and a series of hierarchic decoder transistors, all said transistors having gate terminals connected to respective drive switches;
• a parasitic capacitance connected to a common node between said program load transistor and a first of said hierarchic decoder transistors in said column decoder portion;
• a binary decoder having a signal input and a plurality of outputs corresponding to the drive switches, respectively;
• and
• a precharge circuit connected between one output of said binary decoder and said first hierarchic decoder transistor and receiving a suitable precharge signal to start a precharge phase of said parasitic capacitance.

A memory device, comprising:

• a matrix of multilevel memory cells;
• and
• corresponding row and column decoder circuit portions, each column decoder circuit portion including a bias circuit for biasing a drain terminal of a corresponding one of the memory cells, the bias circuit including:
• a drain voltage regulator producing a regulated voltage for a program load transistor and a series of hierarchic decoder transistors, all said transistors having gate terminals connected to respective drive switches;
• a parasitic capacitance connected to a common node between said program load transistor and a first of said hierarchic decoder transistors in said column decoder portion;
• a binary decoder receiving as power supply said regulated voltage and having a signal input and a plurality of outputs corresponding to the drive switches, respectively;
• a precharge circuit connected between a first output of said binary decoder and said first hierarchic decoder transistor and receiving a precharge signal to start a precharge phase of said parasitic capacitance.