Semiconductor device and data processing system

A semiconductor device comprising:

• a first latch having a pair of input/output nodes;
• a first bit line connected to one input/output node of the first latch and connected with a plurality of electrically rewritable nonvolatile memory cells;
• a second bit line connected to the other input/output node of the first latch and connected with a plurality of electrically rewritable nonvolatile memory cells;
• a second latch connected to the first bit line;
• a third latch connected to the second bit line;
• a first logic combining circuit connected to the first through third latches;
• a second logic combining circuit connected to the first bit line;
• a third logic combining circuit connected to the second bit line;
• and
• a control circuit connected to the first through third latches and the first through third logic combining circuits;
• wherein the first logic combining circuit generates control data used to define to which of first through third threshold voltage states one nonvolatile memory cell is set with respect to a fourth threshold voltage state and to supply the generated data to the corresponding first through third latches, and
• wherein the control circuit is capable of performing program control so as to control the operations of the first through third latches and the first through third logic combining circuits to thereby bring each volatile memory cell to a first threshold voltage state according to a logic value of the control data supplied from the first logic combining circuit to the first latch, bring each volatile memory cell to a second threshold voltage state according to a logic value of the control data supplied from the second latch to the first latch, and bring each volatile memory cell to a third threshold voltage state according to a logic value of the control data supplied from the third latch to the first latch.

A data processing system comprising:

• a control device;
• and
• one or plural nonvolatile memory devices connected to the control device;
• wherein each of the nonvolatile memory devices has a first latch device connected to one ends of first and second bit lines, second and third latch devices respectively connected to the other ends of the first and second bit lines, and a plurality of memory cells respectively connected to the first and second bit lines,
• wherein each of the memory cells is capable of changing a threshold voltage thereof so as to store predetermined data therein,
• wherein a first control circuit is connected to the first through third latch devices, and generates threshold voltage information to be set to the memory cell and sets predetermined information to the first through the third latch devices according to the threshold voltage to be set to the memory cell,
• wherein a second control circuit is provided which controls the setting of the threshold voltage to the memory cell according to control information from the control device, and
• wherein the control device supplies the control information and the data to be stored in the memory cell to each of the nonvolatile memory devices and performs a predetermined control operation.

A data processing system comprising:

• a control device;
• and
• one or plural nonvolatile memory devices connected to the control device,
• wherein the control device supplies control information and data to be stored in each of the nonvolatile memory devices to the one or plural nonvolatile memory devices or performs predetermined processing,
• wherein the nonvolatile memory device has a control circuit and a plurality of bit lines, said bit lines being connected to a plurality of memory cells and information storage circuits, and said each memory cell having threshold voltage distributions of at least three stages and set to any of the threshold voltage distributions, based on information stored in the information storage circuit,
• wherein the control circuit divides the data into at least partial data set by 2 bits, generates control information for determining the threshold voltage distribution of each memory cell, based on the partial data, and supplies the generated control information to the corresponding information storage circuit.