Source line high voltage driver circuit with improved reliability and read performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYue-Der Chih
Life of this patent
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Abstract
A source line high voltage driver circuit 50 for use with a semiconductor memory device which has several other substantially identical circuits 50. Circuit 50 includes a latching circuit portion which selectively applies a high voltage signal to source line SL during a write/program cycle, and a cascode circuit which is used to discharge source line SL and which is formed by two transistors 72, 74. The drain terminal of transistor 72 is coupled to source line SL, and the source terminal of transistor 74 is coupled to ground. The drain terminal of transistor 74 and the source terminal of transistor 72 are each coupled to a node N5 which is electrically coupled to the node N5 of every other circuit 50 within the semiconductor memory device.
Claims19
A source line driver circuit comprising:
- a source line;
- a first circuit portion which is electrically coupled to said source line and which is effective to selectively provide a high voltage signal to said source line during a write cycle;
- and
- a cascode circuit portion which is electrically coupled to said source line and which includes a first transistor, and a plurality of second transistors which are disposed in a parallel relationship, said cascode circuit portion being effective to selectively discharge said source line during a read cycle.
A high voltage source line driver circuit comprising:
- a latching circuit which selectively provides a high voltage signal to said source line during a first cycle;
- a cascode circuit which is coupled to said source line and which includes a first transistor which is coupled to said source line and which includes a first gate, a second transistor which is coupled to said first transistor and which includes a second gate, and a plurality of third transistors which are disposed in parallel with said second transistor;
- and
- at least one control signal which is coupled to said first and second gates and which is effective to selectively activate said first and second transistors during a second cycle, thereby discharging said source line.
A method of driving a plurality of source lines within a memory device, said method comprising the steps of:
- providing a plurality of latching circuits for selectively applying a high voltage to said plurality of source lines;
- providing a plurality of cascode circuits which are each coupled to a unique one of said plurality of source lines, and which each includes a first transistor and a second transistor which are selectively activated to selectively discharge said plurality of source lines;
- and
- electrically coupling each of said second transistors together in a parallel relationship, thereby causing said second transistors to form a virtual ground potential.
Dependencies are inferred from the claim text.