Signal amplifier circuit load drive circuit and liquid crystal display device
AssigneeKabushiki Kaisha Toshiba
InventorsYoshiro Aoki, Masao Karue
Life of this patent
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Abstract
A differential voltage between the threshold voltage of an amplitude amplifying logic circuit 20 and a reference voltage V1 is stored in a capacitor C1. When an input signal IS is input to the amplitude amplifying logic circuit 20, it is input after adding to the voltage of the input signal IS the voltage stored in the capacitor C1. In this manner, any difference between the threshold voltage V1 of the amplitude amplifying logic circuit 20 and the reference voltage can be absorbed. Therefore, a signal amplifier circuit can operate normally even when the threshold voltage of the amplitude amplifying logic circuit 20 in the signal amplifier circuit varies.
Claims10
A signal amplitude amplifier circuit supplied with a digital input signal and outputting a digital output signal, the digital input signal having a first amplitude and the digital output signal having a second amplitude which is larger than the first amplitude, comprising:
- an amplitude amplifying logic circuit including a first node supplied with an internal signal and a second node outputting the digital output signal, said amplitude amplifying logic circuit amplifying the amplitude of the internal signal having said first amplitude to generate the digital output signal having said second amplitude;
- a differential voltage hold circuit including a third node connected to the first node of said amplitude amplifying logic circuit, and a fourth node, the differential voltage hold circuit temporarily holding a differential voltage between a reference voltage of a voltage value for switching said digital input signal between a HIGH and a LOW and a voltage substantially equal to a threshold voltage for switching a logic of said amplitude amplifying logic circuit between the HIGH and the LOW;
- a digital input switch including a fifth node supplied with the digital input signal and a sixth node connected to the fourth node of said differential voltage hold circuit, said digital input switch turning ON to supply the digital input signal to the fourth node under a condition where said differential voltage hold circuit holds the differential voltage, so that said differential voltage hold circuit supplies the internal signal to said amplitude amplifying logic circuit, the internal signal being generated by adding the differential voltage to the digital input signal;
- a threshold voltage setting circuit configured to set the third node of said differential voltage hold circuit to a voltage substantially equal to the threshold voltage of said amplitude amplifying logic circuit when setting the differential voltage in said differential voltage hold circuit;
- and
- a reference voltage setting circuit configured to set the fourth node of said differential voltage hold circuit to the reference voltage when setting the differential voltage in said differential voltage hold circuit,
- wherein said differential voltage hold circuit includes a first capacitor having one end connected to the first node of said amplitude amplifying logic circuit and the other end connected to the sixth node of said digital input switch.
A signal amplitude amplifier circuit supplied with a digital input signal and outputting a digital output signal, the digital input signal having a first amplitude and the digital output signal having a second amplitude which is larger than the first amplitude, comprising:
- an amplitude amplifying logic circuit including a first node supplied with an internal signal and a second node outputting the digital output signal, said amplitude amplifying logic circuit amplifying the amplitude of the internal signal having said first amplitude to generate the digital output signal having said second amplitude;
- a differential voltage hold circuit including a third node connected to the first node of said amplitude amplifying logic circuit, and a fourth node, the differential voltage hold circuit temporarily holding a differential voltage between a reference voltage of a voltage value for switching said digital input signal between a HIGH and a LOW and a voltage substantially equal to a threshold voltage for switching a logic of said amplitude amplifying logic circuit between the HIGH and the LOW;
- a digital input switch including a fifth node supplied with the digital input signal and a sixth node connected to the fourth node of said differential voltage hold circuit, said digital input switch turning ON to supply the digital input signal to the fourth node under a condition where said differential voltage hold circuit holds the differential voltage, so that said differential voltage hold circuit supplies the internal signal to said amplitude amplifying logic circuit, the internal signal being generated by adding the differential voltage to the digital input signal;
- a threshold voltage setting circuit configured to set the third node of said differential voltage hold circuit to a voltage substantially equal to the threshold voltage of said amplitude amplifying logic circuit when setting the differential voltage in said differential voltage hold circuit;
- and
- a reference voltage setting circuit configured to set the fourth node of said differential voltage hold circuit to the reference voltage when setting the differential voltage in said differential voltage hold circuit,
- wherein said threshold voltage setting circuit includes:
- a first switch having one end connected to said third node of said differential voltage hold circuit and another end connected to a cancel terminal that changes linearly from a first voltage to a second voltage when setting the differential voltage in said differential voltage hold circuit, said first switch turning ON when setting the differential voltage in said differential voltage hold circuit and turning OFF when a voltage of said third node of said differential voltage hold circuit is substantially equalized by the threshold voltage of said amplitude amplifying logic circuit.
Dependencies are inferred from the claim text.