US 6,603,446 B1Granted

Plasma display device

AssigneeFujitsu Limited

InventorsYoshikazu Kanazawa, Takeshi Kuwahara, Haruo Koizumi

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Abstract

Disclosed is a configuration of a PDP in which different sustaining discharge signals are applied to odd-numbered ones of X electrodes and Y electrodes and even-numbered ones thereof respectively. Owing to the configuration, the wiring in a drive circuit for driving the X electrodes or Y electrodes is simplified, and a scan driver can be formed with an IC or ICs. A plasma display device has a display panel including first to third electrodes. Sustaining discharge signals that are mutually out of phase are applied alternately to adjoining ones of the first electrodes and adjoining ones of the second electrodes respectively. Consequently, first display cells are defined between the second electrodes and the first electrodes on one side of the second electrodes, and second display cells are defined between the second electrodes and the first electrodes on the other side of the second electrodes. Interlacing where the first display cells and second display cells are allowed alternately and repeatedly to glow for display is carried out. A drive circuit for driving the second electrodes includes a first drive circuit for outputting a pulsating voltage to be applied to the odd-numbered second electrodes, a second drive circuit for outputting a pulsating voltage to be applied to the even-numbered second electrodes, and third circuits associated with the second electrodes for applying the pulsating voltages, which are output from the first drive circuit and second drive circuit, to the second electrodes, and for applying a scanning signal selectively to the second electrodes. In the plasma display device, the third circuits are grouped into third odd circuits to be connected to the odd-numbered ones of the second electrodes, and third even circuits to be connected to the even-numbered ones of the second electrodes. The third odd circuits are integrated into at least one chip, and the third even circuits are integrated into at least one chip.

A plasma display device having a display panel with first and second electrodes arranged in parallel with one another, and third electrodes arranged orthogonally to the first and second electrodes, discharge cells being selected with a scanning signal and an addressing signal to be applied to the second and third electrodes, the selected cells being caused to sustain discharge by applying sustaining discharge signals to the first and second electrodes respectively, sustaining discharge signals that are mutually out of phase being applied alternately to adjoining ones of the first electrodes and adjoining ones of the second electrodes, whereby first display cells, being defined between second electrodes and first electrodes on one side of the second electrodes, and second display cells, being defined between second electrodes and first electrodes on the other side of the second electrodes are interlaced, where the first display cells and second display cells are allowed alternately and repeatedly to glow for display, said plasma display device comprising a drive circuit driving the second electrodes in said plasma display device, said drive circuit comprising:

a first drive circuit outputting a pulsating voltage to be applied in common to odd-numbered ones of the second electrodes;
a second drive circuit outputting a pulsating voltage to be applied in common to even-numbered ones of the second electrodes;
and
a plurality of third circuits, associated with the second electrodes, applying the pulsating voltages output from said first drive circuit and said second drive circuit to the second electrodes, and applying the scanning signal selectively to the second electrodes, said plurality of third circuits comprising:
a plurality of third odd circuits connected to the odd-numbered ones of the second electrodes, and
a plurality of third even circuits connected to the even-numbered ones of the second electrodes, wherein
said third odd circuits are integrated into one or more chips, and
said third even circuits are integrated into one or more chips that are different from the one or more chips into which said third odd circuits are integrated.

5 more elements

Abstract

Claims11