Circuits and methods for latch metastability detection and compensation and systems using the same
AssigneeCirrus Logic, Inc.
InventorShyam S Somayajula
Life of this patent
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Abstract
Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch 209. Detection logic 202a,b 703 detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch 209. Suppression logic 703 generates an output of a selected logic level in response to the detection of a metastable state by detection logic 702/703.
Claims18
Metastability compensation circuitry for detecting and compensating for metastable states of a regenerative latch in a charge redistribution analog to digital converter comprising:
- first and second latches each having a selected threshold voltage for monitoring corresponding first and second outputs of the regenerative latch;
- detection logic for detecting a selected output state of said first and second latches corresponding to a metastable state of the regenerative latch;
- and
- suppression logic for forcing a first output bit of the analog to digital converter to a selected logic level in response to the detection of a metastable state by said detection logic and for maintaining a second output bit at a present logic level.
A method of compensating for metastability in a charge redistribution analog to digital converter including a regenerative latch comprising the steps of:
- for a current bit being processed by the converter, comparing first and second outputs of the regenerative latch against a preselected threshold voltage;
- in response to said step of comparing, forcing an output of the analog to digital converter representing the current bit to a selected logic state when the first and second outputs of the regenerative latch are below the preselected threshold voltage;
- and
- in response to said step of comparing, forcing an output of the analog to digital converter representing a subsequent bit to a selected logic state when the first and second outputs of the regenerative latch are below the preselected threshold level.
An analog to digital converter comprising:
- an array of capacitors;
- a plurality of switches for selectively coupling first plates of said capacitors to an input during a sampling phase and to selected reference voltages during conversion phase bit-cycling;
- a regenerative latch having an input coupled to second plates of said capacitors for comparing a voltage at said second plates of said capacitors against a voltage at a second input of said latch;
- a return path for controlling said plurality of switches in response to an output of said latch;
- and
- metastability compensation circuitry comprising:
- level detection circuitry having a preselected threshold voltage coupled to the output of said regenerative latch;
- and
- bubble suppression circuitry coupled to the level detection circuitry for forcing an output of said analog to digital converter to a selected logic state when the output of the regenerative latch is below the preselected threshold voltage for a current bit being tested.
Dependencies are inferred from the claim text.