Method and apparatus for maintaining clock accuracy at power down

A circuit that synchronizes an output clock signal to a second clock signal, comprising:

• a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal;
• wherein the frequency locked loop circuit includes a frequency discriminator and a controlled signal generator;
• and
• wherein the controlled signal generator includes a counter that provides the output clock signal and an up/down counter, the up/down counter receiving a signal from the frequency discriminator and providing a signal to the down counter.

A disk drive system;

• comprising:
• a hard disk drive;
• and
• a motor controller coupled to and controlling the hard disk drive, the motor controller comprising a circuit that synchronizes an output clock signal to a second clock signal, the circuit comprising:
• a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal;
• wherein the frequency locked loop circuit includes a frequency discriminator and a controlled signal generator;
• and
• wherein the controlled signal generator includes a down counter that provides the output clock signal and a saturated up/down counter, the saturated up/down counter receiving a signal from the frequency discriminator and providing a signal to the down counter.

A disk drive system;

• comprising:
• a hard disk drive;
• and
• a motor controller coupled to and controlling the hard disk drive, the motor controller comprising a circuit that synchronizes an output clock signal to a second clock signal, the circuit comprising:
• a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal;
• wherein the frequency locked loop circuit includes a frequency discriminator and a controlled signal generator;
• and
• wherein the controlled signal generator includes a counter that provides the output clock signal and an up/down counter, the up/down counter receiving a signal from the frequency discriminator and providing a signal to the down counter.