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US 6,603,338 B1Granted
Device and method for address input buffering
AssigneeSTMicroelectronics S.r.l.
InventorDavid C. McClure
Life of this patent
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Abstract
A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.
Claims25
An address input buffer device for an asynchronous device, comprising:
- a first circuit for receiving an address bit signal;
- a second circuit, responsive to the first circuit, for generating a logic true signal of the address bit signal received by the first circuit and a logic complement signal of the address bit signal received by the first circuit, wherein a signal transition of the logic true signal is spaced in time from a signal transition of the logic complement signal, the second circuit includes timing circuitry to place the logic true signal and the logic complement signal in the same deasserting logic state for a predetermined period of time following the address bit signal transitioning between logic states;
- an edge detection circuit for generating a pulse signal that is asserted during the time the logic true signal and the logic complement signal are in the same deasserting logic state;
- and
- a summing circuit including at least one pull-down device, each pull-down device being activated by a logic true signal and corresponding logic complement signal generated by a distinct second circuit, an output node of the at least one pull-down device being connected to a pull-up device, an impedance level of the pull-up device being varied between at least two finite values when activated based upon a signal level of the output node.
2 more elements
A method for buffering an address input signal for an asynchronous circuit, comprising the steps of:
- receiving the address input signal;
- generating a logic true signal representation of the address input signal and a logic complement signal representation thereof;
- separating in time signal transitions of the logic true signal representation from signal transitions of the logic complement signal representation during the step of generating, including the step of temporarily placing the logic true signal representation and the logic complement signal representation in the same logic state following a signal transition appearing on the address input signal;
- generating an edge transition detection pulse during the step of temporarily placing, the edge detection pulse having a pulse width approximately equaling the time the logic true signal representation and the logic complement signal representation are in the same logic state;
- and
- generating a summing signal based upon the edge transition detection pulse, wherein when the summing signal transitions to a logic level indicative of an absence of an edge transition detection pulse, the summing signal is pulled to a reference voltage with a first impedance value and then with a second impedance level a period of time thereafter.
3 more elements
An input buffering circuit for an asynchronous device, comprising:
- a means for receiving an input signal;
- and
- a first signal generating means, responsive to the means for receiving, for generating a logic true signal representation of the input signal and a logic complement signal representation of the input signal, wherein the logic true and logic complement signal representations are initially placed into the same logic state following an edge transition appearing on the input signal;
- a second signal means for detecting an edge transition appearing on the input signal and generating a pulse signal that is asserted during the time the- logic true and logic complement signal representations are in the same logic state;
- and
- a third signal means responsive to the second signal means for generating an output signal based upon the pulse signal, the output signal having a first output impedance level following transition to a logic level indicative of an absence of the pulse signal and a second output impedance level a predetermined period of time thereafter while in the logic level indicative of an absence of the pulse signal.
3 more elements
An asynchronous device, comprising:
- an address input buffer for receiving an input address bus and generating logic true and logic complement signals of each address input signal of the input address bus, wherein a signal transition appearing on a logic true signal is separated in time from a signal transition appearing on a corresponding logic complement signal;
- and
- decode logic for receiving the logic true and logic complement signals of the address input buffer and asserting at least one of a plurality of decode output signals based upon a value of the logic true and logic complement signals;
- control circuitry responsive to the logic true and logic complement signals for generating a control signal having a logic value based upon the presence of transitions appearing on the logic true and logic complement signals, the control circuitry having a pull-up or pull-down device coupled to the control signal and providing a first impedance level initially when in a logic state indicative of an absence of the transitions, and a second impedance level a predetermined period of time thereafter when in the logic state indicative of an absence of the transitions;
- and
- circuitry for performing an operation responsive to a decode output signal being asserted.
3 more elements
Dependencies are inferred from the claim text.