Duty cycle correction circuit

Abstract

A duty cycle correction circuit for a semiconductor memory device capable of exchanging data on both edges of rising and falling of clock by correcting duty error of input clock signal, including a phase detection unit for receiving input clock signals and reference clock signals to generate a phase difference detection signal comparing phase difference; loop filter unit for converting the phase difference detection signal into a voltage signal and outputting the result; multi phase signal generation unit for generating a clock signal having a plurality of phase differences by controlling the delay time of the input clock signal and then, selecting and outputting one clock signal by comparison with the voltage signal; and a duty correction unit for receiving the input clock signal and the clock signal outputted from the multi phase signal generation unit and logically combining them to correct duty of the input clock signal.

Dependencies are inferred from the claim text.